This is more of a question to the "anycpu" forum but I figured out that I might get better replies here.

I incidentally came across this page http://daveshacks.blogspot.com/2015/12/inside-alu-of-armv1-first-arm.html on the reverse engineering of the ARM1 processor, and I got confused about the fact that, as it seems, the ALU circuit does not use any kind of carry look ahead to operate. According to the article, it is made of 1 bit slides which are just chained together with the carry and the zero flag being directly propagated from one bit to the next. This is apparently the circuit:



So, I don't really understand why this does not cause an unacceptable delay on the design. My only guess is that since this was a 3-stage pipelined processor, maybe fetching and decoding stages already took longer, so the ALU was in fact not critical (?)

Any ideas?

The ARM1 did not have caches, so most likely the off-chip memory access is the long pole in the tent.

So, does this imply that, in effect, they didn't really care about the ultimate performance of the ALU?.

Indeed. As long as the ALU is not the slowest part of the design, it doesn't need to be faster.

In practice, ripple carry is still useful for small groups of bits within an overall carry-lookahead design. The lookahead circuitry might make use of the extra Zero signal that the ALU generates.

I notice that the polarity of the Carry output is different from that of the input - so there is definitely something between bit slices, even if it's just an inverter.

According to the article "The eagle-eyed will also notice that the Carry propagation and Zero calculation circuits alternates slightly between each bit, with b0, b2, etc identical, and b1, b3, etc. identical. The end result is the same but the reason for the difference is to keep the execution path as fast as possible by eliminating an inverter per bit; note that the Carry Out and Zero Out signals are opposite polarity to the inputs."

I see. Well there's only two gates per bit in the carry chain, so that's a total of 64 gate delays across the 32-bit word. That seems acceptable if the gate delay is only about 1ns.

Well, having two gates per bit for the carry chain is always the case, so I guess that's not the difference with other designs. It most likely implies that there was no need for a faster ALU in that design.

It is quite surprising that ARM1 has a ripple carry. Even more surprising, the 32 bit barrel shifter executes in the same cycle, slowing down one of the inputs to the ALU. And as far as I can tell (BUT NO!), ARM2 and then ARM3 haven't put in any faster an adder, even though the target clock speed goes up and in the case of ARM3 there's an on-chip cache. (But I may be missing something, and I believe at some point the barrel shifts cost an extra cycle on execution.)

Edit: this presentation says ARM2 has a 4-bit carry lookahead structure.
Edit: and also says ARM1 use of a complex gate means only one gate delay per bit.

It's certainly about balance though: if the CPU and external RAM speeds are linked, and the RAM speed is limiting, the CPU need not be faster and probably shouldn't be, otherwise someone spent some effort and maybe some area or power needlessly.

Some interesting reading if you can find these papers:

Furber, S., & Thomas, A. (1990). ARM3 — a study in design for compatibility. Microprocessors and Microsystems, 14(6), 407–415. doi:10.1016/0141-9331(90)90113-a

Furber, S. . (1988). The advantages of RISC architectures. Computer Standards & Interfaces, 8(1), 29–35. doi:10.1016/0920-5489(88)90073-6

Maybe another factor is that the ARM1 was designed by a small and inexperienced team. Looking at a picture of the chip, the ALU takes up a nice regular rectangular space, lining up very well with the register file and barrel shifter. Adding irregular structures, investing more time, and adding risk of introducing a mistake, was probably not worth it.

I had a similar reaction when I found the ARM1 had a ripple carry, I certainly did not expect it. The barrel shifter does not cost an extra cycle, shifting one operand is an embedded feature of many instructions and these instructions definitely do not take longer.


Thanks for that, It's quite interesting to learn that:

- the ARM1 had a ripple carry (page 21)
- the ARM2 had a 4 bit carry look ahead (from page 23)
- the ARM6 had a carry-select adder (from page 28)

Anyone interested in digging further into ARM1 layout/circuit, send me a PM! (There's a version of the visualARM which is a bit more like the visual6502 than the public version. Some JavaScript skills would be useful, for finding and highlighting signals.)

That rather good technical presentation is one of five by Przemyslaw Bakowski - grab a copy while you can:

An introduction to processor design
An introduction to ARM processor architecture
ARM processor organization
ARM processor implementation
The ARM Architecture

There's also a large and technical book by Steve Furber, "ARM System-on-Chip Architecture" which contains the info about the ALU structure in the various ARMs, along with a great deal more.

Another interesting read on the innards of ARM1, by Ken Shirriff:
http://www.righto.com/2015/12/reverse-e ... or-of.html