You're right! I should read the spec sheet once in a while, eh?

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Bill

Nice!

Just one thought though, is it really a computer if it has no I/O?

Just throw in one more chip, call it 11 and have something that is useful, maybe?

_________________
Bill

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

LOL!

That would definitely cut down on the support calls ...

_________________
Bill

Yup -- it breaks the cycle in TWO places!

No way for garbage to go in, and no way for garbage to get out!

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I can't resist mentioning H G Muller's 'matchbox' chess computer, battery powered, '816 based, no ROM, fits in a matchbox and plays chess:

It looks pretty minimal. I think the program is downloaded into RAM using a ROM in the socket, then retained on battery power.

The 28L92 would also be a good choice for an '816 based system, but it doesn't have the additional active-high select input, and I think I recall seeing in other threads that it can definitely be sensitive to spurious accesses. One solution is to only access it using instructions that have no dead cycles, which I think includes all the long addressing modes (since the carry cycles for indexing are absorbed by loading the high byte of the address). Another side benefit of mapping I/O high!

With six selectors on the '138 available for I/O (four if we reserve two of them to provide a contiguous RAM area), there is no problem whatsoever attaching, say, a 28L92 UART, a DS1511 RTC, a VIA for a local keymatrix and bit-banged SPI to a display, and still have space for additional devices without need for further decoding. Space for all these could be provided on a PCB, and the builder could assemble them in any desired order after the core.

Probably not in the spirit of this challenge, but I think I can reduce the chips quite a bit by making use of a 6530-004 TIM chip, this provides ROM and I/O in one package. The I/O (and here is the cheating) could be used for bank select outputs for the RAM, therefore eliminating the need for the latch on the high address bits, at the expense of eliminating many of the advantages of the 816.

The ROM should work well enough in emulation mode, and provides additional useful features such as a 300 bps serial console port.

I don’t think this would be a very usable system, but it could result in a working 65816 with as few as 5 chips.

While sketching out the details, I found that the 28L92 has an active-high reset line, opposite to anything else in the system. As a workaround without using any extra chips, I'm wiring it up to an output on the VIA.

Meanwhile, the VIA also serves as a Mode 3 SPI master, which can be used to drive a write-only display such as the Sharp Memory LCD. It should also be straightforward to attach a keymatrix to the VIA, allowing for local input and display rather than always going through the UART.

> therefore eliminating the need for the latch on the high address bits, at the expense of eliminating many of the advantages of the 816

Subversive!

Okay, here's what I've worked out thus far. First, the basic core:

Then the peripheral devices; you can probably start with just the VIA, and add the others around it. I've left most of the external connections to the VIA and UART as exercises for the reader:

And finally, the extra memory chips to give a 1MB contiguous RAM area:

All of this relies on just two 74HC-series chips for glue logic, and one more as a bank address latch.

74HC likely won't be fast enough for latching the bank logic.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

You my notice that the positive Phi2 (to the CPU) is actually delayed by one 74HC gate relative to the inverted /Phi2 sent to the latch, rather than the other way round. So as long as the clock speed is modest (as it has to be anyway with a slow EEPROM and no wait-states), 74HC *is* fast enough.

Sorry late to the party, guys and gals.

I have an idea though several details are yet to be worked out. How about using simple I/O address decode logic and selecting both RAM and ROM for memory operations but directing the /RD signal to only one or the other? The idea here is that a switch is set at power-up (reset) to select ROM 'read' and RAM 'write' in order to copy a ROM image into RAM, then the switch is toggled to select RAM 'read' and RAM 'write' effectively mapping ROM out of the address space. With the simple address decoding in the example drawing below, there will be four 32K ROM images spanning the 128K address space when ROM 'read' is enabled.

Another switch might be used to map an I/O block into or out of the address space. Again, the simple address decoding would place the I/O block into each 64K 'bank' but when the I/O block is turned off you have contiguous RAM memory. The example below should scale up to a 256K or 512K RAM chip, as well as a larger ROM or FLASH chip.

I'm not familiar with 65C816 and what it takes to qualify RAM 'read' or 'write' operations. I'm also not exactly sure how to take advantage of the high order address lines (A21..A23) as potential triggers or inputs for the <Read> and <I/O> switches.

Stay safe. Cheerful regards, Mike, K8LH

At the basic level, you can interface the '816 like a 6502, relying on just Phi2 and R/W as control signals. The wrinkles are that A16-23 (the bank address) are multiplexed onto D0-7, so you have to latch them during Phi1 in order to make use of them during Phi2, and that VDA and VPA indicate Valid Data Address and Valid Program Address respectively; if both are high simultaneously, that's a replacement for the SYNC signal. In short, if VDA and VPA are both low then it is desirable to deselect all devices, as it's an internal-operation cycle. Finally, if RDY is low (typically due to wait states) then the bank address must not be latched because the data bus remains in data mode.

All of this is handled appropriately by the circuits I've posted, which you may want to review. With two glue-logic chips and an octal latch, you can have a minimal interface and address decoding which assumes that there are no wait-states (and does not provide any), and does not fully handle VDA and VPA (so every memory cycle is assumed to be valid, except that the VIA is qualified by VDA). With four glue-logic chips and an octal latch, you can have full handling of VDA, VPA and RDY, together with a trick that maps out the ROM when the CPU leaves Emulation mode for Native mode (using the fact that the '816 conveniently presents the E, M and X flag bits on output pins).