6502.org Forum  Projects  Code  Documents  Tools  Forum
It is currently Fri Nov 15, 2024 1:01 pm

All times are UTC




Post new topic Reply to topic  [ 3 posts ] 
Author Message
PostPosted: Wed Aug 05, 2020 1:23 pm 
Offline

Joined: Wed Jun 17, 2020 10:51 am
Posts: 60
Debugging writes to a 74LS574 attached to the 6502 data bus I saw these signals which are a bit different from what I would expect. Here is the clock signal:
Attachment:
clock signal.jpg
clock signal.jpg [ 85.57 KiB | Viewed 396 times ]

Channel 1 is the select line that gets triggered by writes to 0x0340. Channel 2 is the clock pulsing at 500kHz. Here is an example from one of the datalines:
Attachment:
dataline_example.jpg
dataline_example.jpg [ 72.96 KiB | Viewed 396 times ]

Is it normal that while clock signal is 0 the datalines show a slope? If not, any idea where it might come from?

thanks for any answer

_________________
No simulation survives contact with reality!


Top
 Profile  
Reply with quote  
PostPosted: Wed Aug 05, 2020 2:00 pm 
Online
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10979
Location: England
I think that may be as expected: with the clock low, the databus is undriven, and any TTL loads will tend to pull the signals high.


Top
 Profile  
Reply with quote  
PostPosted: Fri Aug 07, 2020 2:00 am 
Offline

Joined: Wed Jun 17, 2020 10:51 am
Posts: 60
thanks

_________________
No simulation survives contact with reality!


Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 3 posts ] 

All times are UTC


Who is online

Users browsing this forum: BigEd and 8 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to: