Alarm Siren wrote:
(You'll want to post a greyscale version of the schematic, or a grumpy BDD will tell you off.)
Feedback:
- Can I suggest bus lines for your address and data busses, to make the schematic easier to read.
- You could use a DS1818 (or something like it) as a single component replacement for your 555-timer monostable reset controller.
- I note you're using the 74AC logic family. Generally on this forum we recommend the 74AHC family instead: it has the same fast propagation times, but has gently edges which are less prone to signal integrity problems.
- The E pin on the '816 is an output and doesn't need a pull-up.
- Some of your memory/rom decoding looks... strange. Do you have an intended memory map we can check against, please?
- ABORT and RDY on the '816 should have pull-up resistors on them if you're not using them.
- Re part U25a, and the note next to it; whilst there's certainly no theoretical problem with using a ROM to decode addresses, I worry that said ROM may not be fast enough - they usually aren't - especially given your 5MHz clock speed.
- X6, the ACIA: there is a nasty bug in the current production run of the WDC ACIAs that make them hard to use for transmitting without tying up your application in a busy-loop. Not impossible to work around, but worth knowing, especially as there are plenty of other UARTs available that are bug free and more capable anyway. Also I believe the current production run of ACIAs require a 1M resistor across XTAL1 and XTAL2 pins. Both the bug and 1M are mentioned in the Errata at the end of the latest version of the ACIA datasheet.
(apologies if any of the above is stuff that's already been covered - this is the first time I've laid eyes on any version of your design)
My software is REALLY Buggy and doesn't behave well when using buss lines, the connections either have to be point to point labels or wire if you want a working PCB to be generated.
i will in update the parts to be the appropriate family and change the 4 bit ram to something like a GAL8V16.
I'm kind of stuck on chaining the ACIA as all my monitor Software relies on this chip to function.
My planned memory map is as follows:
$0-$7FFF RAM
$8000-$9FFF I/o
$A000-$BFFF Propeller 2 Vga Interface ( not in schematic Yet)
$C000-$FFFF 16k bootstrap and BIOS ROM PAGE
$10000-$7FFFF Addon prts 0-7
$80000-BBFFFF Rest of flash rom
$BC000-$FFFFF space for addon ram (connector/ decoding logic not shown)
Hope this helps
Kuzai
EDIT: Thanks to whomever linked the tow post i made about my schematics, if someone could please tell me how to this for the future, That would be Awesome!
Thank you all for putting up with my messy schematics.