The SRAM chip I am using has a Address setup time of ZERO ns before /WE goes low, starting the write cycle.
But, after looking at the timing diagrams, the problem will seem to be bus contention immediately after PHI2 transitions. PHI2 controls which master has the bus: HIGH being the 65c02 and low being a 25 ns GAL22V10. The datasheet specifies a minimum address hold time of 10 ns after PHI2 falls. The GAL22V10 datasheet specifies a minimum time for INPUT to OUTPUT ENABLED of 3 ns. So, the CPU could be clinging on for dear life to the bus, while the GAL is smashing the heel of its boot on the 6502's knuckles. The resulting garbage on the address bus could tell the decoder to select SRAM and if the CPU was just WRITING (/WE low) then SRAM could be corrupted and my day ruined.
Am I right? What are some solutions? The system clock will run at 6.5MHz. I could use a 25 MHz clock to create a quadrature clock and use the first quarter of each phase as a settling time for the signals. The logic would shut off the appropriate bus and then "clock" the address decoding logic. Is that overkill?
_________________ Thanks for playing.
-- Lord Steve
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