Hi guys

As a small side project I'm looking at seeing if I can replace an NMOS 6502A processor with a CMOS WDC W65C02S in a BBC Micro model B (British 8 bit computer from the 1980's).

So far this is what I've come up with (please forgive the image rather than text - was to preserve the formatting - please click on it to enlarge):



Can anyone spot any issues with it?

A few other concerns:
CLOCKS
I'm a bit concerned about the clocks as I remember reading somewhere that WDC doesn't recommend using PHI1O (pin 3) and PHI2O (pin 39) on the w65c02s as these are no longer calibrated / tested properly so may be unreliable? If this isn't the case then I'll connect these pins up. However, if the output clocks aren't good to use then my issue is that I'd need to generated a clock 180 degress out of phase with PHI2 (pin 37), route that to where PHI1O (pin 3) connects to the motherboard and diconnect pin 3 from the CPU. I'll probably just use a 74ACT04 (https://www.ti.com/lit/ds/symlink/sn74act04.pdf) although I don't know if the propgation delay (between 1 and 9ns) would work.

TTL / CMOS LOGIC
I've read a few posts on here which indicate that the WDC 65C02S is quite robust and should be able to pickup incoming TTL signals despite there normally being an issue here. As such I shouldn't need any bus pull up resistors on the processor inputs?

NMI / IRQ
Can I get away with removing the pull up resistors for the IRQ and NMI inputs to the processor to remove the open drain aspet? Could I get away with leaving these in?

BBC Micro clocks (in red) and IRQ / NMI (in green) - click to enlarge:

I think I'd be tempted to hop over to the stardot.org forums https://stardot.org.uk/forums/ and ask this there. There are probably many more people there with direct experience of this. There are funny things on the old Beeb to do with timings and bus loadings so who knows what's best outside the pure 6502 -> 65C02 issues.

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

The lists in the graphic are correct.

Regarding the use of the Ø1 and Ø2 outputs, I suspect the lag between them and the clock input is vanishingly small when considered against the relative;y sedate clock speed of the Beeb. I see no reason to not use them if that's what the original circuit did.

As for the 65C02's inputs, WDC designed the original version of the 65C02 (that is, prior to the addition of the MLB and VPB outputs) to be a drop-in for an NMOS 6502. Ergo the inputs would have to be TTL-compatible in order for it to work. Consider that many Apple ][e owners upgraded their machines to the 65C02 without problems (later on, Apple themselves made the 65C02 standard in the ][e). Also, I can tell you from personal experience that I installed a 65C02 in a PET 8032 for a guy and it worked like a charm. The PET, of course, had the NMOS 6502, as well as a pile of TTL glue logic.

Going off on a slight tangent, a while back I (and others) speculated that both the WDC 65C02 and 65C816 have TTL-compatible inputs, despite what the data sheet would suggest. The reason this came up had to do, if I correctly recall, with discussion over the need for a data bus transceiver and its ability to act as a level shifter (if using 74xCT logic). I pointed out that my POC V1 units were stable at high speeds and that was with an SRAM (ISSI IS61C1024AL-12JLI) and an EPROM (AMD 27C256-55) whose outputs are listed as TTL levels. I don't think stable 12.5 MHz operation (tested at 15 MHz without the SCSI host adapter) would have been possible if the '816 wasn't able to recognize 2.4 volts as a valid logic 1.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Stardot is a good idea.

As for the question of logic levels, I don't doubt BDD had success despite the datasheets' pessimism. Perhaps a WDC cpu will indeed accept a below-spec voltage and still see it as logic high. But it's equally plausible the memory chips output a logic high that's above their published spec. (Maybe both circumstances prevail!)

So, I doubt you'll need pullups, but as long as you stick with WDC there are no guarantees. FWIW, Rockwell and most other 65C02's do guarantee TTL compatibility right in the datasheet. And if you can lay hands on such a chip (there are lots still around) you'll have no pin variances (eg VPB) to account for.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

In our Beeb816 experiments we put an '816 into a Beeb without any special interfacing. See for example the May 2008 photo on this page:
https://sites.google.com/site/beeb816/to-dos/pictures

(I don't remember all the details, by any means. We have put a clock buffer in place - I can't say if that was necessary or just caution, without digging.)

You should be able to just drop the chip in and try it. At 2MHz the clock timing of the modern CMOS part is very uncritical as seen by the old TTL circuitry. And /IRQ and /NMI are both inputs to the CPU, the open-drain stuff just being a way to have multiple interrupt sources without them shorting each other out; the same pull-up resistors will work fine.

Before you do so, however, first check the impedance of Pin 1 of the CPU socket to ground. If it's a short, you'll need to bend that pin out of the way so it doesn't make contact when inserted. That's the only significant hardware incompatibility of the W65C02S with original NMOS parts.

Some software, particularly games, may balk at some quirks of the NMOS CPU no longer being present. In particular there are a few "undocumented" instructions which were never intentional, but result from details of the NMOS implementation and the way opcode decoding was done. In the CMOS devices the opcodes are fully decoded and all NMOS-undocumented instructions are now explicitly NOPs or new instructions. These same games won't run on a BBC Master, because the latter used a CMOS version of the 6502 as well.

In principle there could be problems with a fast part in a slow circuit. For example, a 'C02 might change the address bus rather sooner after the clock falls compared to an '02. If the surrounding circuit has a hold time constraint that's more than minimal, it might be correct for the '02 but fail with the 'C02. Likewise the timing of RnW might be advanced.

Good points, although I am hesitant to accept serendipity as a technical explanation.

What needs to be done is to take static readings of bus voltages to see what is coming out of SRAM when generating a logic 1 (and ROM—most also emit TTL-level voltages). A circuit with single-stepping capability via clock-stopping would make this possible, I'd think. Obviously, YMMV due to temperature, actual Vcc level and the usual chip production variances.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hi guys

Thanks for the replies. I had considered posting on stardot (and may still do so) but decided to post here first.

I've tried a WDC 65C02S 14MHz processor with the following done to it:
- Pin 1 (VPB on 65C02, VSS on 6502A) lifted / disconnected
- Pin 2 (RDY on both) not lifted, but connected to pin 8 (VDD) via a 3K3 resistor
- Pin 5 (MLB on 65C02S, N/C on 6502A) lifted / disconnected
- Pin 36 (BE on 65C02S, N/C on 6502A) lifted / disconnected

Unfortunately it doesn't work. The BBC tries to start with a single tone, but does not actually start executing ROM code. I used a scope on the processor and found the following:

- All clocks look fine
- VDD is at 5V
- RESB (reset) is at 5V
- NMIB and IRQB are at 5V
- SO is at 5V
- Address bus pins are at 1.8V with no activity / fluctuations
- Data bus pins are at 2V to 2.5V with repeated noise patterns

If I put the 6502A back in it all works fine.
I might look at adding a pull up resistor on the data bus pins. Anyone have any ideas / thoughts ?

You probably don't have to lift pins 5 and 36. Seeing as there is no connection on the older 6502s they are likely not connected on the PCB. If in doubt you can just do a quick check on the socket with a DMM, however I've never found a case where these pins were routed to anywhere on the PCB. However pin 36 should be connected to 5V, otherwise the bus may not be enabled.

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Bill

BE is the bus-enable input, which should be tied to Vcc. Unless BE is driven high, it may cause the 'C02 to high-Z the buses, which means A0-A15 and D0-D7 will be floating.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yep that was it. I feel a tad daft for not spotting it - many thanks .

The mod to the W65C02S looks a bit cowboy, but it was the easiest way to do this and I have CPUs to spare .
I also haven't had to modify the motherboard at all so it looks like the open-drain aspect of the motherboard IRQ/NMI circuits isn't an issue.

Well done! (In summary, this substitution is quite straightforward as long as you get all the little details right.)

Indeed. No excuses.

A quick note: This was a nice little diversion, but unfortunately this is probably not a good replacement due many of the unofficial instructions having been replaced with different ones in the WDC W65C02. For standard use this is not a problem, but many of the games on the BBC Micro use those unoffical instructions and so won't work.