the microsemi MT8952B seems to be originally intended as an ISDN x.25 controller for the d-channel and to be interfaced with motorola 6809 controllers (also usually in isdn terminal adapters

it does however seem to do all the things the MC6854 Advanced Data Link Controlle (no longer in mass production), furthermore never was available rated for more than 2mz) also does.

i'd say it's a pretty good candidate for either a bus network topology simple, standardized network to be used with 8 and 16 bit microcomputers and microcontrollers.. (for example when combined with canbus linedrivers)

besides that it seems to have it's uses for packet and tactical radio TNCs (it does the whole NRZI bit stuffing and framing that upon first glance over the datasheet seems 100% compatible with ax.25)..

(besides that it can turn the bitstuffing off and after that it's simply a really fast uart...not entirely sure on the bit order on the line tho. it might not simply be rs232 at a higher bitrate in 'transparant mode' (As for use in econet, i'm not sure wether econet uses NRZI bittstuffing at this point, it most likely does)

(and yes it's 5.25V and pdip and parallel bus and i -think- it should work with 65xxx cpus just as well)

has anyone ever used these things with 65xxx ? or for any other purpose than building isdn equipment? (you can basically chunk out network cards for pretty much any commodore, atari, acorn, etc product at less than 10 dollars each using these chips - it won't be ethernet but those computers can't handle 10mbit anyway and the cs9800a doesn't have workiung irq's in 8-bit mode so this is probably better... 1 or 2 mbit should suffice. 160kbit would even be better than 'nothing'). (as for the tacical radio communications, 1200 baud is still standard, 9600 optional, and 38400 very very fast to this very day

the bus timing in the datasheet seems a bit 'off' compared to 65xx family chips (address and databus lines don't seem to -need- to have the desired state at the same time and for some reason it can be clocked on 'cs' or on 'e' but has no actual 'clock' pin but i guess it should basically just work in a new 65c02 or 65815 board or old microcomputer.

From the datasheet, the MT8952 is supposed to be used with a 6800\6809,
MT8952 bus timing parameters start at page 22 of the PDF.

IIRC the 6800\6809 bus works quite similar to the 6502 bus.

When taking a look at the timing parameters in the W65C02 datasheet starting at page 25,
I think the MT8952 is supposed to work with a W65C02.
//MT8952 tEWH (E clock pulse width HIGH) = 145ns min., with a symmetrical clock and no waitstates etc. I think this would limit PHI2 to ca. 3.4MHz max.

BTW: the MT8952 is, in no way, related to the old MC6852 or MC6854.

In 680x bus parlance, the E clock is equivalent to the 65xx bus Phi2 clock; the 6809 also has a Q clock in quadrature with the E clock, but that's not used here. In that sense, the MT8952 bus interface is basically equivalent to that of the 6522 VIA, and you can wire it up similarly; the only glue logic you need is address decoding. As with a UART or ACIA, there is a second clock input to the chip which is used for the comms line being interfaced to, and has nothing to do with the CPU bus.

It should be safe to run at 3.33 MHz with no wait states (limited by E high pulse width), or 8 MHz with one wait state (limited by E low pulse width for access on consecutive cycles), or 10 MHz with one wait state (limited by E high pulse width) if you can guarantee you won't access the chip in consecutive cycles; this should be straightforward on the 6502, but may require care with an '816. To implement wait states you'll need to insert glue logic before the E pin, to prevent it going high when not selecting the chip, and to prevent it going low in the middle of a cycle.