Same thing as a NAND, drawn in negative logic.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks, that clears things up. I've just discovered that the difference between the schematic numbering and my board is that on D and E, chips 1 do not exist. You should start counting at 2. That "fixes" the numbering so it makes more sense now for the chips to be located where they are. You can see what I mean on the attached pic (from when I washed the board a few days back).

So am I correct in saying that for D8 pin 6 to be high, I need either of pins 4 and 5 to go low?

Yep.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

TI can't remember to had manufactured the 74100 and the 74177.

Found a reference at bitsavers: TI databook 2ed 1976 part7 (21MB)
74100: PDF page 112 (7-113), two 4 Bit transparent latches
74177: PDF page 258 (7-259), asynchronous 1+3 Bit binary counter with asynchronous parallel load. //If QA would be tied to CLOCK2 inside the chip, it would be a 4 Bit counter.



Hmm... in the PET 2001 schematic, for D6 (74177) and D7 (74177):
pin 6 (CLOCK2) is labelled CL1
pin 8 (CLOCK1) is labelled CL2
Don't get confused about this.

//Might happen, that we have to check if E6, D6, D7 are counting.

Check D8 pin 4 and pin 5.

Thanks, they're both at 4.46V.

Do we know what frequency those ICs will be operating at? My scope only has about 200KHz bandwidth, measurements in the MHz range won't be visible to me. I haven't looked at the crystal top left of the schematic, I'm kind of assuming things are ok there because I see lots of healthy clocks elsewhere on the board.

If I have to buy a better scope then that's what I'll do, however, this is the first time in 20 odd years I've needed one so I'm keen not to spend money...

This explains, why D8 pin 6 is low.

E6 pin 4, 8, 9, 18, 17: there is supposed to be a signal at these pins, check if they are stuck low or high.

Basically, we have a 5 input NAND (D8, E8, E5) feeding D8 pin 4.
The E6 pins listed above are the 5 NAND inputs.

Edit:
I think that the frequencies of the signals in that part of the circuitry would be below 1MHz.
Hey, you could try to buy an old/used analog oscilloscope at a flea market or such.
But better check, if the selector switches are still working...

or worse, the aliasing may give you misleading information.

Pleas see what the 6502 primer has to say about it, starting about 2/3 of the way down the Basic Workbench Equipment page. It should help you find what you need, possibly even free, and without buying something you find out too late is totally inadequate.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Ok, just for reference, here are all the pin measurements for E6. Thankyou for helping here, it's great to learn how this all works. As a child I just stared at it and thought it was magic...

E6:

pin 1 = 0V
pin 2 = 1.22V
pin 3 = 1-3V jittery (see pic)
pin 4 = 3-4V jittery
pin 5 = 3.85V
pin 6 = 0V
pin 7 = 0V
pin 8 = 0V
pin 9 = 0V
pin 10 = 0.2V
pin 11 = 0V
**** correction - pin 12 is identical to pin 23 **** pin 12 = 1.950KHz, 0.5s, 1Vrms (pic attached)
pin 13 = 0V
pin 14 = 0V
**** retested pin 15 and it's 0.16V ****pin 15 = 3.85V
pin 16 = 0V
pin 17 = 0V
**** correction - pin 18 is 0.08V **** pin 18 = 3.85V
pin 19 = 3.85V
pin 20 = 3.85V
pin 21 = 15.608KHz flattened sawtooth, 64µs, 3.56Vrms (see pic)
pin 22 = 31.887KHz, 64µs, 1.82Vrms
pin 23 = 15.625KHz, 64µs, 1.4Vrms (see pic)
pin 24 = 5.1V

> E6 pin 4, 8, 9, 18, 17: there is supposed to be a signal at these pins, check if they are stuck low or high

So no signal at 8, 9 and 17. All 0V /edit (and pin 18 = 0.08V, see correction)

So if I read this right, using this pinout of the E6 (74100), pins 3, 4, 5, 19, 20, 21, 22, 23 are all fine. Whereas 8, 9 and 17 are low, which means I should be looking at inputs 10, 11, 12, 15, 16?

Not quite sure why 23 and 12 are different, I'll check again. But they have a signal so I guess I should move onto D7 next.

Just re-checked 12 and 23 and they're identical, along with C2 pin 8, so it must have been a bad reading from me. I've edited the post above.

I did just have a very curious fault on the PSU though, the slow-blow fuse went OC so I replaced that and had only tiny voltages out of the transformer. Checked and re-checked everything, power switch, earth connection, fuse in the mains plug, and once I powered back up the transformer was acting normally again. I think once this sync issue is out of the way I'll double check the transformer connections, make sure it's ok.

The second 4 Bit latch in E6 (74100): //inputs at the left, outputs at the right:
pin 11 (0V,low) > pin 8 (0V,low)
pin 10 (0.2V,low) > pin 9 (0V,low)
pin 15 (3.85V,high) > pin 18 (3.85V,high)
pin 16 (0V,low) > pin 17 (0V,high)

The logic levels at the inputs an outputs of that latch per Bit does match,
so we could assume for now that the 4 Bit latch is working.

But there are no signals, means the counter D7 (74177) attached to the latch does not count.
I'm not sure if the counter D6 (74177) does count as it should, but at least there are signals at some of the outputs...

So check the control inputs of D7:
Pin 1 (/LOAD), pin 13 (/CLR). Those pins are shared with the D6 counter.
Pin 6, pin 8. Those pins are the clock inputs.


It isn't sorcery, but trying to figure out how some of the old TTL circuitry out there works might be a bit difficult sometimes.

Basically, D6 and D7 generate the address for the display RAM.
The amount of characters per line to be displayed isn't a multiple of 2 (not 32 or 64), the latch E6 compensates for this.

It appears that the output of the address counter also is used for identifying
in which raster line the the VSYNC has to be generated (seems to be the logic gates feeding D8 pin 4),
and in which raster line displaying characters has to end (seems to be the logic gates feeding D8 pin 5).

I'll look at D7 now. I was daydreaming the other night, if I won the lottery I'd pay a programmer to create an online tool emulating exactly how the board works, showing you the expected signals, voltages, etc, at every point. With an emulated keyboard too. And I'd get them to allow you to create faults at any point. It'd be of limited benefit but it'd sure put a lot of these computers back in the hands of users...

Well, I'm not into simulating.
But for logic level simulation you could try something like Logisim.

Another option would be getting familiar with, let's say, the Altera Quartus Prime IDE and try to simulate the circuitry in there... for porting it to a FPGA.
//Terasic DE10 P0466 EvalBoard, 10M50 FPGA, 87€. I think a PET would fit into that chip. At least one.

After you have figured out how the circuitry works, write an article about it.
This sure would be helpful for repairing old PETs and putting them back into the hands of users.

Have a nice weekend, will be back next Monday.

Results back from D7:

pin 1 = 15.625KHz, 64µs, 3.4Vrms (pic attached)
pin 2 = 0.16V
pin 3 = 0.08V
pin 4 = 0.08V
pin 5 = 0.08V
pin 6 = 0.08V
pin 7 = 0V
pin 8 = 15.625KHz, 64µs, 3.56Vrms (pic attached)
pin 9 = 0.08V
pin 10 = 0.08V
pin 11 = 0.08V
pin 12 = 0.08V
pin 13 = 15.625KHz, 64µ, 4.05Vrms (pic attached)
pin 14 = 5.11V

So it seems to be getting a good consistent clock, but nothing on inputs 3, 4, 10 and 11, and therefore nothing on outputs 2, 5, 9 and 12. Am I getting that right?

Ok E6 I've miscounted E6 pin 18 and muddled it with 19. Pin 18 is 0.08V, as shown at D7 pin 3 (which it's connected to). Sorry, E6 is a big chip, I must have lost count.