One step to try might be to pare it down further, if you're comfortable with that. You have a lot there that's not necessary. For example, the data sheet says, "The reset input clears all internal registers to logic 0 (except T1 and T2 latches and counters and the shift register). This places all peripheral interface lines in the input state, disables the timers, shift register, etc. and disables interrupt from the chip." So the only setup you need it to make port B (PB) all outputs, by writing FF to DDRB. Then decrementing PB, regardless of where it started from, will cycle all the bits, bit 7 being slowest, cycling about every 2/3 second at 1MHz, 1/3 second @ 2MHz, etc., plenty easy to see with a flashing LED.
Code:
* = $8000
.cpu = "w65c02"
;;; via1 device addresses:
via1base = $6000
via1rb = via1base+0 ; write output register b, read input register b
via1ddrb = via1base+2 ; data direction register b
nmi:
irq:
;;;
;; coldstart - initialises PB as all outputs.
;; (The rest is taken care of by the RST-low pulse.)
;;;
coldstart: .block
ldx #$ff
txs ; Initialise stack pointer register
stx via1ddrb ; and make PB0-PB7 all outputs.
;;;
;; Test code for toggling PB7 (and other bits too, but faster), endlessly
;;;
loop: dec via1rb ; PB7 will cycle high & low
jsr delay ; at about 2/3 second at 1MHz, PB6 at
bra loop ; twice that rate, PB5 4x that rate, etc..
.bend ; (That's plenty easy to see with an LED.)
delay: .proc
ldx #$ff
loop2: ldy #$ff
loop3: dey
bne loop3
dex
bne loop2
rts
.pend
* = $fffa
.word nmi ;NMI
.word coldstart ;RESET
.word irq ;IRQ
The 65c02 can be single-cycled; so using a single-cycle circuit like what's 3/4 of the way down the
clock-generation page of the 6502 primer, you can stop at each phase-2-high time and probe around looking at logic states and looking for voltages that are not a solid logic high or low, indicating bus contention. (The power supply's current meter might also tell you that when you get to the troublesome cycle.) WDC's W65C02S allows you to stop in either phase of the clock, not just the phase-2-high time; but you will still need to debounce.
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