When CA1, CA2, CB1 or CB2 are used in input mode as described in 1.4 of the Data Sheet (See table 1-5) they are always edge sensitive (negative or positive active edge). I am using CA1 in input mode to control bit 1 of the Interrupt Flag Register as illustrated in Fig 1.1 of the Data Sheet. The problem with W65C22S is a too high sensitivity. I am transmitting data over a standard 1.5 m long computer cable with 8 threads for data bits and 2 threads for CA1/CA2 control. Due to induction ("cross-talk") I keep getting false triggering of this bit when many data bit change in the same direction at the same time. This seems to be a serious draw-back of the chip. Are not other user having this problem? Sometimes these false triggerings can be identified and "masked out" by the software but a real "hardware solution" would be much preferable! Good ideas welcome!

Remember WDC's VIA has CMOS inputs. They're high-impedance, and do not offer the TTL or LSTTL loads that other VIAs offered. The CMOS input is a big advantage for many things, and I'm glad they finally did it that way. The part is also much faster than its predecessors, including the rise times of driven lines. If you're having problems from that, you could put a resistive and/or reactive load at the input to absorb high-frequency signals arriving there from capacitive or inductive coupling over a long line. But it would not be appropriate to permanently put such a load on for all applications. My own workbench computer feeds the printer with a WDC VIA, through 20 feet (6 meters) of normal printer cable, with no problems.

What about connecting the control line that is in input mode (CA1,CA2,CB1 or CB2) to +5V over a condensator? Obviously one has to test this out! Upper limit defined by what the other chip can source to produce a sufficiently steep pulse , lower limit defined by the need to get rid of the false triggerings of the very nervous W65C22S. But in what range should one start experimenting?

There are several ways you could do it. A 220-ohm resistor between the line and the VIA pin, along with a 220pF capacitor from the pin to ground would give you a time constant of about 50ns, which may do the job of absorbing the transients you're getting from the long line with parasitic capacitances and inductances. I don't think I'd want to go any higher than that to start.

Ideally the long lines would have controlled impedances with at least twisted pairs if not individually shielded conductors. That would accomplish a couple of things. One is to avoid crosstalk. The other is that terminating at least the receiving end with the characteristic impedance of the line avoids reflection of the fast edges that produces the echos. Since you probably don't that luxury on a cheap printer cable, just terminating with resistors alone will not be enough (unless it just pulls a line up or down that doesn't have a good connection at the sending end, but that should be fixed). Putting just a capacitor alone at the sending end may slow the edge down enough to avoid the problems we've been discussing, but may cause other problems for the IC trying to drive the capacitors in addition to the line.

RS-232 line receivers have some hysteresis to avoid the problem. In fact the 1489 IIRC has a pin that lets you change the amount of hysteresis. The 1488 line driver data sheet had instructions for adding capacitors to slow the outgoing edge down to levels that would not cause problems. In extreme cases you could precede the VIA input pin with another IC with hysteresis built in. That might mean one with Schmitt-trigger inputs or making your own circuit with a comparator so you can control the amount of hysteresis as well as the response times.

An IC without hysteresis is not in itself considered "nervous". The reasons they don't build hysteresis into all digital inputs is that it increases the price and slows the part down. Look at the propagation delays of the 74xx04 (hex inverter without hysteresis) to those of the 74xx14 (hex inverter with hysteresis) and you'll see the latter is quite a bit slowere (maybe about half the speed).

If the reader is not familiar with hysteresis, I'm sure I can find explanations on the web for what it is and what it is useful for. Probably any CMOS logic data book would have a section about it in the front.