Yikes! I was getting so used to "Everything works at 1MHz" that I wans't even thinking about propagation delay. Of course you're right, CD4048 if off the table now, 74688 takes its place. I had already looked into it... to be part of TOD, to compare current time with the ALARM value.



Yup, many unused gates/input pins in my first schematic, as I try not to overcrowd it with "function-less" stuff. When I'm satisfied with it, a tie all floating input pins to GND or VCC, depending on what it needs. On multi-gate ICs, I also connect unused gates, just in case. BTW, I'm using 193 counters, not 192, but they don't exists in my Eagle Library and since they have the same pinout....

I'm off for vacation in September. My plan is to complete and test the design for the timers, and place the order for the PCBs just when I leave. So far, the count bit of the TIMERS feels quite good. I'm having some small issues with the TOGGLE output. It supposed to go high whenever the timer starts, but right now, still not working. Should be an easy fix though. Could even be an issue due to my awful breadboarding habilities

Hmm...
Timer B output > comparators > UNDERFLOW > U6D > TBUND > U7C > STARTCLEAR > U3A pin 1 > START

It could happen that the comparators are generating spikes which clobber down the START flipflop U3A by accident,
and maybe you won't see them with a logic analyzer.

Please check, if the START flipflop goes cleared by accident.
If this is the case, try to check by adding a "low pass filter" if spikes generated by the comparators are the problem:
insert a 470Ohm resistor into the STARTCLEAR line which goes to the U3A flipflop pin 1,
put a 470pF capacitor between U3A pin 1, and see what happens.

...Maybe you need an additional flipflop clocked by PHI2 in the UNDERFLOW signal for getting the spikes out.


Always carry some paper and a pencil around with you while you are on vacation,
just to make sure you won't forget an idea that unexpectedly pops up in your forehead before vacation is over.

Analysis of the typical propagation delays in the timer + comparator section:

there _will_ be considerable spikes on the UNDERFLOW signal.



Edit: HCT192 in the picture, should have been HCT193, sorry.

I'm trying to get my head around the propagation delay for the 4 counters+the comparators. Something in my mind keeps telling me it should be OK, but I know I can't dismiss your advice.

Here are my thoughts on this.

I am counting down, with U21 being the 4 LSB, and U24 the 4 MSB. 74193 is synchronous, so, within each nibble, the outputs will change in sync.

Let's say we're in the last 16 ticks of the counter. U24, U23, U22 already at 0000, U21 at 1111. Outputs from U24,23,22 and U28 will be stable long before U21 reaches 0000. As it's synchronous, there's no danger of it glitching the UNDERFLOW signal. Delay from PHI2 rising edge to UNDERFLOW would be 23+14=37 ns, with no risk of glitches.

I need the underflow signal to be raised before the falling edge of PHI2, as the read operation taking place at that time, should already see the counters reloaded. The UNDERFLOW signal goes through 2 NAND gates, 1 NOR gate, and the time the 193 needs to be reloaded. That's 7*2+8+20=44ns. 81 in total. At 1MHZ, I have 500ns, so plenty of room. 5Mhz would already be pretty tight though.

Back to the glitches... when can they happen? If U21 goes from 0001 to 0000, all other counters should already be stable at that point. Next tick, U21 goes to 1111 (If there hasn't been an overflow already) and the DN clock propagates to the other counters.

I'm pretty confident this won't be an issue at 1MHZ. I'm also pretty sure almost everything I'm doing would need a serious rework above that... but anyway, so far so good.

About the TOGGLE output, it was an easy fix. The TOGGLE output goes high whenever START goes high, and It's cleared on a RESET. U11B takes care of this, but I needed something to detect the rising edge of START. U12A does this. START is the clock input, and D is tied to VCC. The problem was on the /CLR signal of the flip-flop which was connected to PHI2. Easy fix. START changes right after the falling edge of PHI2, so it was immediately cleaned. Changed that to /PHI2 and now it's working.

The output of U21, U22, U23 and U24 doesn't change at the same moment.

If a 74HCT193 counter has a typical propagation delay from "count down input" to "underflow output" of 14ns,
the output of U22 will change 14ns (37ns-23ns) later than the output of U21,
the output of U23 will change 28ns (51ns-23ns) later than the output of U21,
the output of U24 will change 42ns (65ns-23ns) later than the output of U21.
//the output of U21 changes 23ns after DN0 triggers the "count down input" of U21.

I think the 74HCT688 comparators are fast enough to notice those differences in the timing.
A change of the U21..U24 outputs will cause a change in the UNDERFLOW output... with some delay.

If a 74688 comparator has a typical propagation delay from A,B to Q of 14ns and from /E to Q of 9ns,
we are getting a response at the UNDERFLOW output after DN0 clocks U21:
U21: DN0 to UNDERFLOW = 37ns = 23ns+14ns
U22: DN0 to UNDERFLOW = 51ns = 37ns+14ns
U23: DN0 to UNDERFLOW = 74ns = 51ns+14ns+9ns
U24: DN0 to UNDERFLOW = 88ns = 65ns+14ns+9ns

In other words, when DN0 clocks U21,
37ns later the UNDERFLOW signal can't be trusted for a time window of 88ns-37ns=51ns.

Somebody please correct me if I'm wrong.

BTW: The "typical" propagation delay is different from the 'real' propagation delay,
because the 'real' propagation delay depends on temperature, output load, supply voltage...
and on what the manufacturer did when building the chip.


WOOT.

The last post before my well-deserved vacation

I'm about to place the order for both TIMERS PCBs, along with a big batch of ICs, so I can assemble them right when I'm back

I'm not 100% they will work, but right now, the best way to do it is to fully test it.

Meanwhile... SDR and ICR are starting to take shape on paper at least. They will probably fit into a single board. And once I have TIMER and ICR... that should be pretty much enough to run most C64 software. Who needs TOD anyway? I didn't even know it existed until a year ago anyway!

See you all in a few weeks!!

You never know, that's the point.

Maybe you could use 74HCT190\74HCT192 BCD counters for implementing the BCD clock.

Try to recover a bit while you are on vacation, because after the battle is before the battle.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This is it, let's say, end of Season 1.

Luggage is ready, and the orders for the PCB and Components for both timers are placed, so I'll have plenty of work to do when I come back.

Don't worry about TOD, even though the C64 doesn't make too much use of it, my OCD won't let me stop until everything is done, so I'll definitely do it. It will be a tight fit on a single board, I may try placing components on both sides of the board, even though that will make routing quite difficult.

Initially, I had planned to use BCD counters for the TOD for obvious reasons, but I haven't found them in any provider, they're probably more than obsolete. '193 binary counters are easy to find and quite cheap on the other hand.

So far, it's being a very nice trip for me. I've learned quite a few things, remembered a lot of stuff I used to be very good at, that was pretty much forgotten. Also, no C64 have been harmed in any way, which is more than I expected when I started this project a year ago.

But on top of it, it feels extremely nice to become part of this community and be able to contribute back, even if it's just a little bit.

I'll be back in October! Thank you all!

Mouser or Farnell still might have some 74HCT192 on stock... but if the stock is gone, it's probably gone for good.
C64 contains two 6526 chips: better stick with the binary counters, you might want to build another TTL 6526 next year.

Edit: the 74HC192 BCD counter still seems to be available, but be aware that 74HC has a logic level threshold of half the supply voltage (74HCT and 74LS have ca. 1.3V).
//74HCT output driving 74HC input is supposed to work. 74LS output driving 74HC input needs a pullup resistor.
Nah: to be on the safe side, better stick with the binary counters.


You are welcome. Nice progress with your project, and you are no longer a beginner.

Travel safely.

Looking forward to the start of Season 2.

You should be able to use 74HC parts, as long as their inputs are sourced from CMOS outputs rather than TTL. If you need to connect the counter directly to the CPU bus, you can insert a buffer to make that so. It's not necessary for *every* part on the board to be 74HCT.

Skinning the CIA:

viewtopic.php?f=1&t=5695#p70256

And here we go again!

After a week recovering from Post-Vacation Syndrome, and going through a tonne of long-delayed work... it's time to keep going with my little project.

As expected, boards and components for both timers were awaiting in my mailbox when I arrived. I'm only missing the binary counters, which I'm sourcing from a local store and should be here in a week or so. Anyway, I'll assemble every else during this weekend.

I haven't done any real progress during this month, but I do have a rough outline for all remaining units, TOD, SDR and ICR. Falling on the optimistic side, they could be ready to build before end of year.

Meanwhile...



This is soooo great! Just at first glance I (think) I've managed to identify where in the die are all the major components.

Each DDR/PORT bit seems to be arranged just around the pin pads
On the lower half, I've spotted an structure repeated with this pattern 4-3-4-3-4-4, with no doubt, this is TOD (4 bit and 3 bit counters for the seconds/minutes in BCD, and so on)
Above that, on the right, 5 repeats of the same pattern. Those are the 5 interrupt bits.
On it's left, 8 bits, probably for the SDR.
on the upper half, 8+8 bits on the left, same on the right. Hello timers!
Around the timers, a bunch of stuff, probably for the CREGs.

Of course, just an educated guess... but seems to make sense. It will be nice to try to dig a bit deeper into it.

Cheers!

Welcome back.

Looking forward to see, how the 74HCT6526 adventure continues.

The microscopic pictures of the 6526 silicon look very nice,
after they went polygonized we are supposed to be able to reverse engineer the circuitry.
//It won't translate well into TTL, of course.

Looks like the chip was manufactured with a 2µm HMOS II process.

I have the same feeling I had when I completed the first board..



There's no way this will work. There're too many things that could fail. However, I was wrong that time. Let's hope for the same.

I'm just waiting for the '193s. You can see the empty spots on both boards.