Has any tried any kind of IRQ expansion system??

What I want to do is provide a 'seperate' IRQ for each expansion slot - up to 8 maximum. Then some how (this being the bit Im stuck on ) catch the IRQ's in a 8-3 encoder and also trigger the uP IRQ\ line. The uP would then read the 8-3 encoder and get a byte value indicating which lines were active and execute the routines for each interrupt handler.

It would work fine if only one interrupt could ever occur at once, but I expect that more than one interrupt could occur within a clock cycle. So how could I go about 'latching' the 8-3 inputs so it doesnt lose any interrupts??

It needs some kind of resetable buffering so that once an interrupt occurs, it stays active-low until the uP has handled it and reset the line.

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The 65816 (dunno about the latest 6502), has a "Vector Pull" line. Basically, it goes low during an ISR address fetch. So, could basically feed your 3 bit Interrupt number into a small EPROM along with the output of a flip-flop to select the low/high bytes of the word as needed. Or, if you don't mind a range of addresses, hardwireup as follows.

Vector Pull goes low, write $I0 to the data bus, where I is the interrupt you just generated.
Falling edge of CLK2, write $FF to the data bus. A couple of 74XX buffers would do this job very nicely, along with a flip-flop. Just use Vector Pull to enable the buffers, using the flip-flop to select which one.

Thus, your interrupts would execute as follows:
IRQ0 = $FF00
IRQ1 = $FF10
...
IRQ7 = $FF70

That gives you 16 bytes of your ROM to acknowledge the IRQ and jump off somewhere. Of course, it's quite possible that the Vector Pull line never got added to the 6502. Tho, the microcontroller version has lots of ISR entry points, suggesting that the needed logic is available on the silicon, just never brought out to pins.

The further alternate solution is to switch to the 65816. If you do not use the address bus during PHI2 high, it behaves almost exactly like a 6502, at least going upon the ease of dropping them into existing 6502 designs.

What I planned to do was have a single ISR routine in the standard place which, rather than handling the IRQ's directly, would read the 8-3 encoder and the jump to the appropriate ISR's routine.

There would only be 1 IRQ line per expansion card, and it would be up to the individual routine to handle it. The actual ISR stored at $FFFx would simple go to a 'redirector' of sorts.

Assuming the IRQs were all handled via the NMI pin, the process would be something like : NMI low -> NMI ISR ( read 8-3, jmp to appropriate handler, return) -> end ISR -> continue execution

Ok, hmm, even easier, then...

IRQ lines sit HIGH normally, feed them to a 3-to-8 encoder, which normally sits at the value of 7.

Feed the outputs of the 3-to-8 encoder to a 74HC374 octal D-latch as well as a 74HC10 (three input AND gate). Connect the output of the AND gate to the IRQ# of the 6502 and the clock input of the '374 through an inverter. Tie the upper 5 bits of the '374 high (you'll see why in a moment).

When one of the IRQ lines is pulled low, the 74HC10 goes low in response. This puts a low signal into the IRQ line and interrupts the CPU. It also causes the 374 to latch the interrupt code into itself.

Then you just need to have your memory select logic activate the Output Enable of the '374 when you read the location where you want the interrupt # to show up. Hit the resulting value with an EOR #$FF and the bits tied to 1 go away, and you have your interrupt # left over!

Hmm, after writing that, I see your point about latching in each new interrupt. It's almost a simpler design to simply have 8 flip-flops rather than trying to 'encode' it into 3 bits. Just set (or reset) each flip-flop, put the combined bits onto the data bus through a 244, and trigger interrupts with a unlatched set of AND gates. You can get 4 input AND gates that will keep the chipcount down.

Also, look at CPLDs. The smaller sizes come in PLCC44 cases, and you can get PLCC44 to DIP sockets that require no surface mount soldering.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?