DCLK then goes to the Dot Clock output buffer...





...where some creative tinkering with propagation delay and duty cycle also seems to be done.

Dang: looks like DCLK actually is low_active, please change/fix this when drawing a clean set of schematics.

We are through with the official part now...

But wait: there is a defunct bonus level hidden inside that old video game.

Here be dragons.



From what I gathered so far, there is some dead\unused circuitry in the 8701R2,
with Pin 4 as input, and Pin 10, 11 as outputs.

The datasheet only tells you, that Pin 4 is GND and that Pin 10, 11 are NC,
and it basically seems to be right.

To me, the whole thing looks like a "conceptual test run" for some chrominance modulator circuitry.
See, there was some empty space on the 8701 silicon, 8701 had unused pins, and color clock was present in the 8701 anyway.
8701 probably was manufactured in a HMOS-2 process.
IMHO adding some test circuitry for something to be built later with a HMOS-2 process to an 8701 and disabling it
in a later revision of the chip might be cheaper than designing an entire chip for "rocket testing" and then packaging it.

Somebody please check, which came first:
8071 manufactured in a HMOS-2 process, or a CRT controller (like the VIC-II) manufactured in a HMOS-2 process.

To me, those boxes labeled with a question mark don't make much sense. Some open traces in there.
And I would strongly recommend to check if some buried contacts are missing there in the polygonized images.

Edit: shift register is build from switches and inverters. Felt a need to update the schematic after counting those inverters again.

We have a clock generator.

The input of the clock generator had been connected to the /color clock signal in a previous revision of the silicon,
but now it's tied to GND instead.

Means: the clock generator is dead.



;---

There are two shift registers, which were clocked with that clock generator:



Two dead FETs which seem to be leftovers from a previous revision of the silicon.
Also, we have a FET where the gate probably wasn't connected to GND_Osc from the start.

;---

At the output of every shift register, there is an XOR gate feeding a transparent latch:

Like I had said above:
to me the circuitry between the XOR_gates\latches and the output drivers for Pin 10, 11 doesn't make much sense.
I'm not even sure, if it had worked at all.
Maybe buried contacts are missing in the polygonized images, because they are really hard to spot in the microscopic pictures.
Some traces in that area which go to nowhere, maybe some part of the circuitry went removed before revision 2.
Maybe the circuitry has never worked at all, who knows...

...And that's why I didn't see the need to waste any more time and effort with it.

;---

But the output drivers for Pin 10, 11 just seem to be XOR gates with boosted outputs:



They are placed differently on the silicon to make better use of the space available,
but to me the circuitry for the Pin 10 and Pin 11 output drivers looks identical.

woah...

Hi Yann,
and welcome to the forum.

What got me started into digging through old NMOS silicon was the dissection of the famous\infamous SID.
...plus reading introduction to VLSI systems, Mead & Conway 1978.

Oh, yes, welcome Yann! (YG is famous over on hackaday.io and probably elsewhere.)

Famous ? me ? c'mon...
BTW: flattery will not work with me

Sure it will. Those are GREAT shoes!

The problem with getting famous is, that you usually are the last to be informed about this.
An indicator might be that cracker\spammer **** which tends to increase in a non_linear fashion
with famousness until building/creating cool hardware stops making sense anymore...

Edit: sorry for getting a bit upset here.

;---

But back on topic:
Initially, chip layouts went routed "manually".
As "workstations" went faster and more powerful, as CAD tools went into use,
and as the number of transistors on a chip had started increasing too much,
the old school art of "manually" routing a chip layout eventually went extinct.

What makes dissecting old "manually" routed chip layouts that interesting is,
that the designers were quite good back then, with routing, and with logic design.
They had pulled the one or other trick not mentioned in the school books for keeping their layouts
as compact as possible for making good use of the available space on the silicon,
for keeping the cost of them chips as low as possible.

For instance, if you try making a _compact_ PCB layout nowaday, at some point it becomes necessary
to modify the schematic for simplifying the traces on the PCB, like swapping the input pins of a logic gate,
or swapping the logic gates of some 7400 chips, or the pins of a 74245 buffer, or the address lines of a RAM etc.,
or making use of two spare inverters and a spare NOR gate when you lack an AND gate.
In the end, your schematic turns out to be just "the documentation" for the PCB layout.

With old NMOS chips, it could be worse: shift registers working as counters and such,
creative use of trace capacitances and FET switches for implementing transparent latches, etc.
Also, the software tools available for exctacting something like schematics from microscopic pictures
of chip layouts won't bring you far when there are impurities in the silicon and when the designers
did something different from just cobbling together standard cells with CAD tools.

Hmm... actually, digging into old silicon feels a little bit like Kinder Surprise:
Some chockolade around the thing, a nice puzzle to solve, something to toy with...
...just don't swallow the plastic parts by accident.

Since we now have sorted the parts inside that "surprise egg":
after fixing some little errors up in the thread, now the (partially) assembled toy:

A simulation for the 8701 logic in Borland C 2.0 DOS which seems to work.


I'm not much of a coder, of course.

pulse delayer\stretcher drawn a bit differently:



;---

And now for a (very simplified) block diagram of the 8701R2:



We have an oscillator with an external crystal.
// In theory, it could be possible to leave pin 13 open, and to feed a clock signal generated by a TTL "metal can" oscillator through, let's say a 100Ohm resistor, into pin 14.

Oscillator input is feeding the color clock output buffer which emits the color clock at pin 8.
Oscillator input also is feeding a clock doubler, which then feeds that clock generator generating the PHI1 and PHI2 signals used for clocking "the rest" of the 8701 latches.
//Note, that "delta t" here is differently for NTSC and for PAL.

Then we have a LFSR counter which counts 7 steps for NTSC and 9 steps for PAL.
The counter is feeding three big logic gates (and some smaller stuff not shown in the picture at the gate inputs).
One of the gates clears the counter with the 'dinA' signal.

The other two gates generate the signals '#3P' and '#OP', which are active for only one counter step.
Those two signals then are delayed/stretched, then ORed together (actually, it's a big NOR gate instead of an OR),
to get that ca. 8MHz dot clock. (I'm simplifying things here a bit).

The resulting signal isn't symmetrical: 3T high and 4T low for NTSC, and 4T high and 5T low for PAL.
And that's why we have a little bit of trick circuitry in the dot clock output buffer which is "supposed" to make the dot clock "nearly" symmetrical.
The circuitry is a kludge, of course, because the "delta t" time delay at the input of the final OR gate is not different for PAL and for NTSC.
//it isn't an OR gate in the silicon, of course, I'm simplifying things a lot here.
//
//If I would be designing something like this, I would try to get the PAL dot clock symmetrical because it's faster than the NTSC dot clock.
//I suppose the delay is 0.5T, 14ns or such... As a result, the NTSC dot clock would be less "symmetrical" than the PAL dot clock.

;---

And that's all.
If you have success in building a "8701 equivalent" with PFGA, CPLD, PAL and\or TTL, please post schematics and pictures in the forum.

Looks like I won't be able to visit the forum quite often in the next 6 months for job related reasons,
but I think I might have some free capacity in mid 2019.

A call for help:
If anybody happens to have polygonized\annotated pictures of the layers in the 6526 or VIC-II silicon by then,
I would try to grind my teeth into them.

The problem here is, that I'm not good at making polygonized\annotated pictures from microscopic images of chip silicon,
and that making polygonized\annotated pictures really takes a lot of time and effort... and practice\experience.