Hi,

My current board dumps everything out to 3 connectors without any buffers (and somehow works at 10 MHz) and I'd like to change this.
I was thinking of buffering everything with a couple of 74AC245's, the ones for address bus/control signals should always be enabled which is easy.

I was thinking that the data buffer OE could be controlled by the peripherals themselves and that this could be done in a couple of ways
Have each card drive a signal (lets say /DBEN) then use an AND gate with pull-ups on the inputs to drive the data buffer OE or wire-OR the signals to control the OE
I'd prefer the latter as it'd mean one less IC needed on the main board and it could be done simply by driving /DBEN through a schottky diode on each card. the BAT54 apparently has a reverse recovery time of 5ns. would this be quick enough?

I also would like to be able to inhibit the on-board RAM/ROM for things like peripherals with their own memory or rom and was thinking either creating another signal called /INHIBIT in the same way though now I think about I could probably configure the CPLD so that /DBEN always inhibits RAM/ROM etc.

Should /DBEN go through a flip-flop clocked by PHI2 to prevent bus contention?

Does that make sense? will it work?

Only a brief and more general answer, details would require a schematic do discuss upon:

If you insert buffers into any (DB and/or AB) bus, you implement a delay. This means shorter access times and narrower timing margins. It may also mean (depending on the actual layout and loads) signal distortions due to reflections at unterminated ends, higher noise, more radiation (EMC). Using 74AC logic means very fast edges aka lot of trouble if not designed very carefully.

You talk about 10 MHz or so - that means you are using a WDC CPU. This CPU has strong (meaning a lot of driving strength) bus drivers. I would dare to attach 20 to 30 CMOS parts (RAM, ROM, IO) with no buffering at all - the bigger problem would be keeping the traces short! That is why some people favor mezzanine constructions over slots or bus like constructions: shorter overall signal traces = lesser signal distortions.

Unless you are willing to deal with a bunch of difficulties - detecting and dealing with them requires some higher quality equipment and perhaps more than one round in rearranging the pcb layout - I would recommend: avoid it.


Regards,
Arne

The detail very much depends on what you want to do with the expansion slots.

These days with modern chips, there is rarely any need for memory to be on a separate card. So I advise against this. Reserve the expansion slots for I/O only.

It's quicker for the "motherboard"/CPU board to generate the appropriate chip selects rather than incurring a longer delay while the address bus signals have to travel to the most distant card, then the logic on this card has to decode the address, then send a signal back to the "motherboard"/CPU board to enable the data bus buffer... So this means that what will work for a slow system will be next to useless for a faster system.

Even better, implement a "slow bus" for the expansion slots. That is use a 6522 to provide eight address lines, and an eight bit bidirectional bus, along with some control signals.

Mark

In my use case I have a system with on-board CPU/RAM/ROM/IO but experimenting with things like a video card & soon a floppy controller.
The Video card will inhibit on-board RAM as it has it's own Dual-port memory and I also plan to inhibit the onboard ram so I can make a rom card etc.

I'll keep on trucking with current system with slots as I already have some cards that work with it and it seems to work