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 Post subject: 6510 AEC?
PostPosted: Fri Oct 13, 2017 7:27 pm 
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Location: Seattle
Hi All,

I ordered a bunch of 6510's off of eBay but I'm somewhat confused whether the 6510 only tri-states the address bus or also the data-bus and control signals.. The datasheet seems to contradict itself in a number of places:

- AEC is only connected to the address bus buffers in the diagram.
- Whereas the 'Address Enable Control (AEC)' section states:
The Address Bus, R/W, and Data Bus are valid only when the Address Enable Control line is high. When low, the Address Bus, /W and Data Bus are in a highimpedance state. This feature allows easy DMA and multiprocessor systems.

The latter would save me a buffer and some time but there seems to be very little documentation...

Thoughts?

Yvo


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 Post subject: Re: 6510 AEC?
PostPosted: Fri Oct 13, 2017 9:34 pm 
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yzoer wrote:
Hi All,

I ordered a bunch of 6510's off of eBay but I'm somewhat confused whether the 6510 only tri-states the address bus or also the data-bus and control signals.. The datasheet seems to contradict itself in a number of places:

- AEC is only connected to the address bus buffers in the diagram.
- Whereas the 'Address Enable Control (AEC)' section states:
The Address Bus, R/W, and Data Bus are valid only when the Address Enable Control line is high. When low, the Address Bus, /W and Data Bus are in a highimpedance state. This feature allows easy DMA and multiprocessor systems.

The latter would save me a buffer and some time but there seems to be very little documentation...

Thoughts?

Yvo

I'm going on 30-year-old recollection, but I believe the 6510's address bus, data bus, and R/W are put into in the high-Z state when AEC is pulled low. This behavior is similar to that of the WDC 65C02, although AEC in the 6510 is BE in the 65C02. Incidentally, this signal must not be floated—at the minimum, pull it up to Vcc.

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 Post subject: Re: 6510 AEC?
PostPosted: Fri Oct 13, 2017 10:06 pm 
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Thanks!

That kinda makes sense as just floating the address bus alone doesn't. Also the datasheet mentioned the time to float the data-bus. It's just all a bit of a mess..

Once I get my batch in I'll run a couple of tests to confirm and will post the results here.

Yvo


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 Post subject: Re: 6510 AEC?
PostPosted: Sat Oct 14, 2017 1:51 am 
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What is it you are building that requires the 6510?

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 Post subject: Re: 6510 AEC?
PostPosted: Sun Oct 15, 2017 3:33 am 
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BigDumbDinosaur wrote:
What is it you are building that requires the 6510?


I'm interfacing it to an Altera CPLD (EPF7128S to be exact) which is TTL and want to do phase 1/2 sharing, which requires the CPU / CPLD to have access to the bus every half CPU cycle.

While the WDC versions have a BE input, they're CMOS so I'd have to add level shifters which I'm trying to avoid and keep the count to a minimum. The integrated I/O also helps :-)

Too bad you can't find 2- and 3mhz versions on ebay though!

Yvo


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 Post subject: Re: 6510 AEC?
PostPosted: Sun Oct 15, 2017 3:43 am 
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yzoer wrote:
While the WDC versions have a BE input, they're CMOS so I'd have to add level shifters which I'm trying to avoid and keep the count to a minimum.

You could still use a WDC processor and run it at 3.3V. At 3.3V it will still go a lot faster than a 6510. Unlike the NMOS, it'll run down to 1.2V.

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 Post subject: Re: 6510 AEC?
PostPosted: Sun Oct 15, 2017 3:57 am 
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Something to consider :-) Thanks!


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 Post subject: Re: 6510 AEC?
PostPosted: Mon Oct 16, 2017 3:40 am 
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yzoer wrote:
While the WDC versions have a BE input, they're CMOS so I'd have to add level shifters which I'm trying to avoid and keep the count to a minimum.

Actually, it appears that WDC's data sheets may not be entirely accurate in that regard, and that the 65C02 and 65C816 inputs are TTL level (except the clock input, which must be driven rail-to-rail). I can attest that the 65C816 will work with SRAM that has TTL level outputs, and at high speeds, as proved in my POC V1.1 unit at 15 MHz.

Furthermore, consider that the 65C02 is a drop-in replacement for the NMOS 6502. It would not work in that capacity if it required inputs to follow CMOS logic levels.

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The integrated I/O also helps :-)

At the cost of some zero page locations. You can simulate that with a CPLD and some well-thought-out logic.

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Too bad you can't find 2- and 3mhz versions on ebay though!

The 8502 will run at 2 MHz and has the I/O ports present in the 6510.

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 Post subject: Re: 6510 AEC?
PostPosted: Mon Oct 16, 2017 6:32 pm 
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8502's are like hen's teeth! There's only one seller on ebay that charges $12/piece. Anyone know where I can get them / get them cheaper?

As for the IO lines, yeah... It's easy to add that to the CPLD but then I'd have to add another '245 to buffer the output. I'll see.. First thing is to see if the 6510 tri-states all lines. The disable / enable time is listed as an eye-watering 120ns time btw...

-Yvo


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 Post subject: Re: 6510 AEC?
PostPosted: Mon Oct 16, 2017 8:28 pm 
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yzoer wrote:
First thing is to see if the 6510 tri-states all lines. The disable / enable time is listed as an eye-watering 120ns time btw...

Given that the 6510 was designed to operate at 1 MHz, 120ns is quite reasonable. It's part and parcel of with working with an old piece of silicon. I like the 6502 family, but I prefer to have things happen a bit faster, if possible, than what you will realize with the 6510. :D

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 Post subject: Re: 6510 AEC?
PostPosted: Mon Oct 16, 2017 9:29 pm 
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Yeah, I guess you can say it comes with the territory...

On the flip side, you can cram quite a bit of 'useful work' in the time available. Given that I'm using a 24.576mhz main clock and dividing that by 32(!) to get a cpu clock of 0.768mhz, I have 16 clocks available during the first phase. Of course, 6 of those are gone waiting for the bus to tri-state and get back but hey... that still leaves me with 10 clocks!!!!! :-)

Yvo


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