Hi guys

I'm still working on my 65C02GPD v2 design, having "fun" routing it all atm .
While looking at the datasheet for the MCP7940N (I2C RTCC which I plan to incorporate) I noticed that it recommends surrounding the 32KHz crystal/can used for timing with a pour which is grounded.
This should encompass the oscillator circuit entirely (see below) and no traces should be run underneath (same layer or any other layer).

Is this something that I should be doing for my main PHI2 source? I tend to have that as a DIL socket-ed can which then runs to a D type flipflop. I.e. should I be doing away with the socket?

I also found some advice which says that if this is done I should put a pour underneath the can on the top layer (this is a layer 4 PCB - middle two layers are GND and VCC) and on the bottom layer, link both to the GND layer then solder the chassis of the can to both pours.
If so, is capacitance an issue here?

Again, is this something that you guys tend to bother with? I assume to avoid noise on the PCB from the crystal/can?

This is what I've done with regards the RTCC so far:


IC7 is the MCP7940N
The red dotted somewhat asymmetric area is the top layer pour which is linked to the ground plane via the cathodes of the two capacitors C10 & C11. I haven't yet added a bottom layer one.

Any thoughts/advice welcome

Crystal impedance is very high, in the tens of thousands of ohms, even at its series resonance. What they're trying to prevent is capacitive coupling of other signals into the crystal circuit which could upset the oscillator's operation. Most of digital work is low-impedance; so the greater coupling problem is inductive, with transmission-line effects; but this one might be considered more like audio which is high-impedance and where shielding is for preventing capacitive coupling. In the case of the oscillator can however, it's all self-contained within the can which totally shields it from everything. So you don't need such guard rings if you use the can.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for advising Garth.
I'm not at all good with analogue electronics (to my own detrimient), but are you saying the following?
So by not routing signals underneath the crystal you're avoiding affecting the crystal from the capacitance in the signal traces? or is the capacitance developed due to have one above the other?
Again, sorry for the lack of understanding.

With regards to using a can: I'd love to, but my PCB is so crowded that I've gone for a standard crystal for now.once I get the rest of the routing done I can see what I squeeze in.
The PCB restriction is down to using a version of EagleCAD which limits me to 160mm x 100mm. Already had to bring the VIA count down from 4 to 3.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Good point with regards the space. I made the initial decision at the design stage, but I'll convert it over to a half can as you suggested. Going by the data sheet all I need to do is connect X1 and leave X2 floating. BTW the Q1 actually came from the symbol in Eagle so very odd!

And thanks for the further explanation. I think I understand it now (at least basically). I'll still avoid running any traces beneath the can in any case.

[edit] Here's the new layout: