Hi, everyone.

I've been working for a few days now on my first dive into digital electronics (with the help of some friends of mine) and I've come up with what I think is a workable idea. It's got a 65c02, 32k of memory and 8k of ROM in the upper 8k of the address space. It's got a 6551 and a MAX232 for the console. The I/O space is mapped into the upper 128 bits (8 banks of 16 bytes each) of the first 32k. The latter 32k is portioned into 8 8k banks.

You can check out the prelimimary schematic at http://opus.dyndns.org/~chris/board.pdf

Keep in mind when you look at this schematic that not all wires have been drawn, but the basic idea is here. I wanted to post it to get some comments/suggestions from everyone. What do you all think?

Cheers,
Chris

I just noticed that the pdf went to two pages for some reason. If anyone has eagle, they can also see the schematic with:

http://opus.dyndns.org/~chris/main.sch

The diagram doesn't show up for me, but my hunch is that your address-decoding logic is unnecessarily complex, judging from your description above. You can do the whole job with a singe quad NAND gate IC (like 74HCT00) like in http://www.6502.org/users/garth/project ... chematic=2 . This works great if you don't need more than 32K of ROM and 16K of RAM or vice-versa, and the smaller propagation delays from having fewer levels of logic will let you run the computer faster. Here I have 32K of ROM and 16K of RAM, but a small change could turn that around so you'll have 16K of ROM and 32K of RAM. This method allows your 6522's and 6551's to total up to ten in quantity. You can use one of the NANDs with the inputs tied together (or one input tied to Vcc) as one of the inverters in the diagram. The other inverter in the diagram is not needed. It was for something I changed my mind about, and I ended up not using its output. You can see this computer at http://www.6502.org/users/garth/projects.php?project=1

I've only had time for a quick look at your circuit, but I did spot a problem. You don't seem to have connected the Phase 2 signal at all. This signal is vital for correct timing of data transfers in 6502 systems, and you must connect it correctly. For instance, it should be used to control the OE signal of the EPROM and RAM chips. It must also be connected to the Phase 2 input of the 6551.

I think on your diagram, the pins are actually labelled PHI2, but that's the same signal.

Hope you can get your circuit working! I'm building something very similar, using the same set of chips.

I think the reason why the pins don't quite jive is that I was using the W65C02 chip from a user-contributed Eagle library. I just looked over the datasheets and found what I think you're talking about...you're saying that CLK0 should be the system clock and that CLK1 should control OE on the EEPROM, RAM and the PHI2 on the 6551?

I'm hoping that I get the circuit working too...it'd prove that I actually do understand what I've been told.

The clock source (sometimes a crystal can oscillator's output) goes into phase 0 (pin 37 if you're using the DIP). Phase 2 (pin 39) goes to the 6551's, 6522's, and into the RAM-select logic. Phase 1 (pin 3) is left unconnected in most simple 6502 computers unless you hang an RC or crystal right on the processor itself for an oscillator instead of using an external reference.

I tried again to see your schematic. After downloading it, the computer just sits there and gives me a blank white screen. Is it something that won't work with Acrobat Reader 4.0?

I used ps2pdf to convert it from postscript to adobe...the man page says that it produces Adobe version 1.2 output, which is supposed to be compatible with Acrobat 3 and higher. I can try to convert it to a gif if you like...