I'm not sure if I can explain this very well, but I've got a bit stuck trying to figure out how the 6502 works internally. The core of the problem is that there are some cycles where a value is read and then immediately used in the next cycle. I can't see how this can be done unless latches/registers can be passed through immediately? There are many examples of this, but one of the simplest is an indirect read, something like LDA (d) where the address is read from d (low byte then high byte) and then in the next cycle that address is used to read A. JMP is probably an even simpler example.

I'm using the 6502 block diagram as a reference here, and have read through Dr Jefylls visual guide to bus timing to ensure I understand when things happen.

The problem is that on some cycles a program byte is read, this will be latched into DL on the negative edge of phi2 (at the end of the cycle). Now the next cycle starts and may use this value immediately as an address, so it needs to be latched into ABH at the start of the cycle.

So I'd expect that this would require some time to latch into DL then put on the ADH bus and subsequently latched onto ABH, but that can't be the case because it would take too long. This appears to expose a gap in my understanding of the hardware.

The only explanation I can think of is that when the data bus contains the value the DL can be enabled to 'pass through' the value onto the ABH and then the value can be latched simultaneously into DL and ABH. Is this possible?

The block diagram shows that DL is latched on phi2 and ABH is latched on phi1 (assuming that this is falling edge of phi1 which is the same as rising edge of phi2), which adds an extra complication. I'm not sure what this means, but the timing diagrams imply that DL is latched on the falling edge of phi2. Now I'm really confused as that implies that ABH is latched on the rising edge of phi2, but Dr Jeffyls diagrams show the address bus becoming valid soon after the falling edge of phi2.

Does anyone know what really happens here?

You've hit on the answer right there -- often the data can be passed through immediately.

It's only possible for a verbatim copy -- IOW, when there's no intermediate processing required. For example consider a LDA zero-page instruction (which is three cycles). We fetch the opcode, the operand (ie, the z-pg address) and then right away we fetch from that z-pg address. The processor input the z-pg address at the end of cycle 2 then output it early in cycle 3.

With LDA zero-page,X it's a different story. We fetch the opcode and the operand... and then a dead cycle occurs, during which X is added to the operand. Only after that intermediate processing can the fetch from z-page occur.

Offhand I don't know what internal data path is used. But you could confirm that with a look at the visual6502 simulation.

cheers
Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

jds, I have not paid a lot of attention to the internals, but I think you're thinking too much in terms of edge-triggered registers. Think instead in terms of transparent latches, similar to the 74xx573 which lets the data through like a simple buffer when the enable input is high. Then when it goes low, the output is maintained at whatever it was just before the enable went low. I know there were a lot of pass transistors used in this way in the NMOS 6502, where a transistor was turned on to let the data through, and then to latch it, the transistor was turned off and the circuit capacitance held the last driven value. The transistor could let data go either direction, similar to a 4066 analog switch IC. The 65c02 (ie, CMOS) is undoubtedly a little different, more complex, since it allows the clock to be stopped without losing data that was held only by capacitance on the NMOS version.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Okay, that sounds right. (I assume DL and ABH are the proper names. Like Garth, I don't pay much attention to the internals.)

I agree the byte is latched into DL "on the negative edge of phi2," but this wording carries a double meaning which perhaps is what prompted Garth's remarks. DL is a transparent latch, like a 74xx573, as Garth explained. It either continuously follows the changes on its input or else it freezes, holding whatever value was present when the following ended. So it's accurate to say the byte is latched into DL on the negative edge of phi2. However, DL is not an edge-triggered register. (An edge-triggered register never continuously follows.)

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for the quick info. A transparent latch is new to me, so I've learned something today. Seems obvious now when I look at the diagram that DL is called a latch rather than a register. From a quick look around the diagram it is the only latch, even the instruction side of the data bus is called the Predecode Register.

So as a simple summary, the input data latch will latch the value of the data bus on the falling edge of phi2, holding that value until phi2 goes high again. If the ADH bus enable line is high then during phi2 high the ADH bus will reflect the data bus, and phi2 low it will be the latched value at the transition.

So for my case where I need to use a value from the data bus right away, as long as the bus enable is on for ADH then the data value can be latched into DL and also stored in the ADH register at the same time.

I'm trying to accurately model the 65C816 in software and this is the sort of thing that exposes gaps in my knowledge. If I model the timing and also only allow data to flow where busses are on the diagram I should get an accurate reconstruction. It becomes a puzzle of what can be done on each clock cycle. It's interesting what they managed to pack in. There does appear to be some cases where a cycle could be saved on the 65C816 but has been kept for 6502 compatibility, it's a pity they had to do that as the 65C816 could have been even faster.

I've built my model with a 16-bit DL, which now I think is a mistake, but it does make things a lot easier. I'll have to go back and fix that. Looking closely at the 65C816 it is still very much an 8-bit processor in some ways as having an 8-bit bus forces that constraint. A true 16-bit 65xx processor would be an interesting thing to see.

You're welcome. As for the terminology, you need to be cautious because it's not entirely reliable. Broadly speaking, a "register" is just a small, local memory. It's true, people often use "register" to imply edge triggering, but be aware that a transparent latch can also be considered a register. (The situation is somewhat better regarding the term "latch" -- it probably means a transparent latch.)

Yes. But I'm less certain regarding what you said about ADH. The address bus updates during PHI2 low, whereas the data bus updates during PHI2 high. And a similar pattern permeates all the CPU's internal behavior -- many of the latches are transparent during PHI2 low, and many others are transparent during PHI2 high. That's what allows an orderly execution of events -- passing the ball from one hand to the other, so to speak. It's like an assembly line. There are other analogies, I suppose -- a game of checkers, perhaps. You need one half to stop while the other half proceeds, because having both simultaneously active would result in mayhem.

Which diagram are you referring to? There's some good reverse-engineering out there, but the so-called block diagrams found in manufacturers' datasheets tend to be fanciful works of fiction produced by the Marketing department.

Yes, it seems a tragic waste. I summarized some of the details here.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

(crossed in the post!)

Indeed, the 6502 is made of transparent latches - it has a two-phase non-overlapping clock and so pairs of latches can be used to make flops. But also, for example, a signal can go through two phi1 latches before landing in a phi2 latch, which is the sort of thing you see here, with ADH1:
http://visual6502.org/JSSim/expert.html ... &zoom=12.4

But note that you can do this with edge-triggered flops. If, for example, you place your flop close to the output for address bus bit 8, that means you need a purely combinational path, involving some muxing, to get input from data bus bit 1 to that point. What you can't afford to do, because there isn't time, is to place two flops between the incoming data bus and the outgoing address bus.