Congratulations: initial PCB Layout looks nice.

Just a thought:
Maybe it would have been better to route the central GND\VCC traces in the middle of the PCB
(going North between U39 and U40) instead of at the left edge of the PCB (U10).

To me, space between the ICs looks good when using small ceramic capacitors,
it's also possible to have the ICs on top of the PCB and the capacitors at the bottom.
(In my projects, I sometimes had placed the capacitors below the IC sockets).

Using SMD capacitors at the bottom of the PCB also might be an idea.

It's an interesting question, if you want to put those ICs into sockets.
If you do, don't save money on the wrong end and buy precision sockets.
(There are precision sockets with capacitor integrated, but I think they would be too expensive.)
BTW: back in 2009, I had two defective TTL chips fresh from the factory.

Would recommend to have 14 pins instead of just 4 pins for the oscillator Y1,
either by changing the package or by creatively adding some vias.
This way, you sould solder a 14 pin precision socket into the PCB,
then plug different oscillators into it for speed testing etc.

Hmm... that button South of Y1 looks like a reset switch, discharging an electrolytic capacitor.
Maybe it would be good to have a resistor between switch and capacitor to limit the current.

If you happen to have enough free space between U10\U11 and the electrolytic capacitor,
you could place a big diode there (anode connected to GND, cathode connected to VCC),
that short_circuits the power supply if it would be reversed by accident.
Maybe SB560... or a TVS diode...
Another trick to prevent the power supply from connected in the wrong way by accident
would be making P1 a three pin screw terminal with VCC in the middle and the other two pins GND.

There seems to be some free space in the South East edge of the PCB,
would suggest to place a "field of vias" there.
If something in the CPU won't work as intended, this would give you a chance
of "bread boarding" a little circuitry with three chips or so for trying to fix it.

For the oscillator, you could use milled SIL headers, and chop off four individual sockets. MXO45 can oscillators have pins that can fit into those.

The layout is a balance between space and good routing. I try to fit this in 20x25cm.


SMD would decrease signal path options due to shorter pad space.


Yes I definitely will do!


Relevant point. I haven't resolved oscillator socket problem yet, but definitely I need to have socket there. Firstly because I need to have an option to feed manual pulse during debugging as well.
SIL pinheader added. (DerTrueForce message noted)


It is delayed reset upon startup. It is supposed to be there without a resistor. For discharging there is already a resistor due to input pulldown.


Good safety feature. A diode added.


That's a neat idea in deed! I have added a breadboard area. But... of course it would work right after connecting power supply. They always do.. right?

Tiding up signal paths and doing (more or less cosmetic) finalization takes forever. I guess I just need to end somewhere and place an order. I could spend the rest of my life with a board like this...

Axel.

Hmm...

If it would work right after connecting the power supply, you need to be worried...
because this means that all the problems will show up later.

Hey, if it won't work at first try, and if everything that could go wrong goes wrong,
you have a nice opportunity for developing a better understanding of your circuitry,
for digging deeper into it, for further optimizing/improving it...

Clear text: usually, the first PCB always is for the trash can, but please don't get discouraged by this.

Don't read my reply too seriously
I have drawn PCBs for 25 years as a hobby. I know what you mean... I know...

Axel.

The first release candidate is ready and PCBs are under manufacturing. After testing and debugging some final adjustments were needed. The latest schematic diagram is attached. I think I managed to resolve the "reset release in the middle of clock phase" issue and now TTL CPU always starts by executing startup routine first. It includes fetching reset vector and jumping to that address. Opcode $00 is being used either for Break or startup routine depending on /Ready signal fed to microcode ROMs among other input signals.
Thank you all for support! I wasn't sure if this project goes further breadboard...

Looks like 65C51 and 65C22 are available. Also considering 16550 - the good old war-horse

Ciao all,

Axel.

When the autorouting is done, perhaps you can add more ground connections cutting across areas that don't have them anywhere close, on the vertical blue traces.


You could also put thru-hole capacitors on the back (if there weren't room on the front), using the same holes and layout, if necessary. SMT is nice in that it only takes room on one layer, not every layer, so it allows routing through the same space on other layers. OTOH, vias may take extra space since they can't be in the pads if you were going to use automated assembly. (My own memory modules have holes in the SMT pads though, because I knew I was going to assemble them by hand.) SMT pads can be smaller than thru-hole pads, but you can't get a trace between pads of an 0402 (or smaller) chip capacitor unless you go to traces too narrow for economic board manufacture.


I don't see a diagram; but just make sure the switch isn't directly across the capacitor such that it gets a zap of current when you push the button, since that will shorten the life of the switch.


I don't know what family of ICs you're using, but if it's like 74HC, there are protection diodes at every input, so you'd have hundreds of these across the board, and each pair has a lower turn-on voltage than a silicon diode has, meaning a reversed power supply, if it can supply enough current, may start blowing input-protection diodes before the big silicon diode is conducting much.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Just finished some debug boards to be used with mainboard. From top left: IR value+Phase nibble (leds), Databus value, Clock generator (manual feed or clock 0-800Hz), Status leds (SR+Ready+etc)


Routed side of PCB - in case of interest...


Axel.

One step closer to the next milestone.


Axel.

A short summary:

* 16 addressing, 8 bit data
* Mainboard has 72 chips; Mostly 74LSxxx, 3 ROMs for microcode and 1 for FLAG control
* NMOS 6502 compliant instructions. Indirect JMP bug fixed
* Reset and interrupt vectors in original locations
* 5 custom opcodes (INA, DEA, THX, TXH, HLT). First two for INC, DEC acc, THX and TXH to deal with high byte of SP pointer (as easy it would be to implement more custom opcodes I'll probably stay in these)
* No decimal mode
* Memory map (based on current extension boards)
E000-FFFF ROM
DE00-DFFF IO
xx
000-7FFF RAM
Memory location between RAM and IO is for future use (if this project continues). Mostly likely that would mean a VGA adapter and VideoRAM in unallocated area.

* One IRQ line (level triggered)
* 1.37A current (mainboard with 7-segment debug displays)
* Extension port signals: 16-bit address, 8-bit data, /WR, PHI2, /IRQ, /Reset, /Ready
* Prefetch opcode at the beginning of the instructions (calculation of return address saved to stack should be the same as in NMOS 6502)
* single input clock; internally generated four clock signals. One clock cycle == one microcode step
* why this project? for fun
* anything special on this project comparing to other previous ones? nope, I made this my way
* what's the total cost? way more than I expected

ciao,
Axel.

I've learnt something: 74LS245 has horrible power consumption. Depending on output state one ship loads min 48mA (up to 65mA). (That is 0,3W heating element and they are operating HOT!).
The mainboard has 14 of them.
By changing those to HCT-version the load drops from 1,37A to 770mA.

Axel.

That building process was fast, and the result looks nice.


Yep, from my own experiments I remember it has.

BTW: the NMOS 6502 datasheet from 1976 says,
that the power dissipation of the chip was 0.25W typ., 0.7W max.
That would be 50..140mA at 5V.

Status update: (the image says everything I think...)

Quite a lot is going right, I think. Well done!

Did you implement the ROR instructions?
Early NMOS CPUs didn't, later NMOS & all subsequent versions did.
If I recall correctly, OSI BASIC mostly runs without them, but floating numbers are broken.