Hey, all. Been following the conversations here for a while. Anyway...

I'm building a custom board based on the PLCC version of the WDC65C265; once I get it all working, I'll post the gerber file. For the moment, I'm building it out on protoboard. Thus far, I have the built-in ROM Monitor up and running with a UART to USB FTDI on UART Port 3, as required by the Mensch Monitor. I consider this the "debug mode". I'm standing on the shoulders of a giant with the custom ROM I'm working on, using the ROM hack put together by Andrew Jacobs to write to the FLASH ROM. Here is the issue:

I want to expose the Parallel Interface Bus (PIB), see the datasheet at Pages 32 and 48.
http://www.wdc65xx.com/wdc/documentation/w65c265s.pdf.

However, two ports of the PIB Bus (pins 2 and three - see Datasheet on Page 41) are multiplexed with edge interrupt inputs which are used on UART Port 3 and used for DTR and DSR. See also, Page 47 at 3.12-13.

My questions are:

1) To use the PIB, must I disable the Edge Interrupts on those pins (P56 and P57), enable PIB, then disable PIB and re-enable the Edge Interrupts each time I want to employ the PIB; or

2) Is there some other way to use these functions at the same time and share the pins? In other words, are these pins duplexed?

The documentation is a bit unclear.

Thank you!

Jon

PS Might an external device on the PIB be able to enable the PIB itself, on demand? See, "Figure 2.10-1 PIB Registers" on page 32.

Hmmm...

I don't have any '265 experience, Jon, but my hunch is, you'll have to do things the hard way. When designers decide to make a pin(s) multi-function, they're trying to imagine and satisfy umpteen different scenarios their customers might face. And that alone is hard enough. To me, it seems too much to suppose that they'd anticipate and accommodate what you are hoping for -- ie, an accelerated means to rapidly change configuration on the fly with respect to one specific function.

I personally find the PIB very intriguing! Myself, I would have no hesitation in simply abandoning the alternative pin functionality.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hey, Jeff!

I totally, totally agree! I don't really care about the handshake functionality on the ACIA and I certainly don't want to be constrained (by the built-in monitor) to 6.144mhz. But, the boot sequence on it is really complicated (and they even acknowledge that in the monitor documentation... see page 14 here: http://www.wdc65xx.com/wdc/documentation/265monrom.pdf). And that is a big obstacle.

Jon

PS Does anyone know how to dump the built-rom (w65c265's 8k) into a file I could transfer to my Windows machine?

Hi Jon,

While I haven't yet implemented a PIB interface I know a little about it. For starters, the Mensch mask rom uses the PIB pins for functions other than the PIB i.e. handshaking for the UARTs and with the SXB board bank switching of the flash rom. If you wanted to use the UARTs with handshaking add a 6521 or 6522 to CS0B or CS1B and write a custom monitor for CS4B. The internal rom can be switched out with BCR bit 7.

I don't think it's safe to enable the edge interrupts on the PIB pins while the PIB is active.

From the data sheet only the 65c265s can activate the PIB. One might come up with some protocol for a peripheral to request that the PIB be activated and a session on it to begin.

The mensch monitor supports reading and writing of S28 records on the UART ports for transferring data.

The edge interrupts on the UART ports are supposed to be multiplexed so that depending on the rising or falling edge of the clock the signal is either data on an RX pin or an edge interrupt.

That's about all I know...

Cheers,
Andy

This is a reply more than an answer.

The problem with the '265s is that it's more a proof of concept that an end product.

The included ROM monitor is there just as a sort of bootloader and to show something once you have the chip working.

When you code your own software and disable the internal monitor. You can then use whatever resources the chip offers, including, as handyhandy said, attaching an external UART by using the system bus and disable the internal monitor, so you can use all the chip ports as you would like (except for system bus ones).

But what WDC actually wants with this chip is the developer to use it for designs a MCU would be ideal for. And once you have all the code and your project done, you would contact them and ask for a way for you to include your code in the mask rom in a custom design to be put, running on hundreds or thousands of chips.

One of the advantages of this last way of operating is that you can have all the system bus converted to input/output individual pins, because all the code would run in internal memory.

The other thing that you can do with this chip is disabling completely all of its internal features and keep only its 65c816 core with a full 24 bit address bus that is not multiplexed at all. But then you would have to add all the communication features you want as external chips. And for DIYers, that's (for me) the real value of this chip: the only '816 chip with the full address bus exposed.

It's a persuasive viewpoint, tokafondo. If we shift our thinking and look at the '265 as more or less just a CPU chip then that "CPU" is quite competitive with the '816.

It's a shame that nobody (AFAIK) has tried overclocking the '265 to see how fast it will go. Although the doc suggests it's a lot slower than the '816, in reality it may be just as fast...

... or, in terms of speed vs design effort, even faster. We know the '816 can be dramatically overclocked, but as the frequency goes up the design challenge associated with multiplexing rises sharply. It's no small hurdle that the address/data bus is required to complete two tasks every clock cycle.

I suspect it may be comparatively easy to design an overclocked '265 system whose speed rivals that of an '816 system that was considerably more difficult to get working smoothly and quietly at high clock rates.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The fact that the chip can be clocked up to 8Mhz is because WDC did only certificated up there.

The monitor and internal comms hardware only works up to 6Mhz.

But nothing stops anyone to try to clock it higher if using external chips.

If one was to turn off CS2B that would pretty much disconnect all of the internal I/O and ram from the core 65c816. The only way I can conceive of reconnecting the internal I/O and ram is reset.

Cheers,
Andy

P.S. Bill Mensch has a number of patents relating to his micro-controllers. I usually use patents.google.com and do a name search like William Mensch or his full name William Mensch Jr.

I wish that was the case, but I have a 6.144mhz oscillator connected up to FCLK, and it doesn't work, i.e., the ACIA Port 3 displays garbage output. By their own datasheet, 6.144 is in-spec for the monitor.

I hardwired a 1.8432mhz oscillator to Timer 4 via P60. Does anyone have any idea how to use this to set the baud rates for, say, Port 3? I know to switch Bit 0 of the Timer Control Register to "1" to use that as TIN. Beyond that, I'm not sure what to do. The documentation isn't clear as to which registers need to be set.

My board works at 4.9152 with support from the chip and monitor themselves.



That's why external memory, comms and logic chips are needed. Once you have code running on external memory you can turn all the internal resources off and have the internal CPU working only with what it can manage with the system bus, like a standard '816 does.

I think p. 48 of the data sheet is pretty clear on the use of TIN/TOUT, i.e. when the UART is not in use Timer 4 can be used for said purpose similar to a 6522. While there are 4 UARTs there are only 2 timers and it’s up to you to define which timers control which UART.

P60-P61 would correspond to rx/tx on UART0. P62 can be either rx on UART1 or pulse width measurement (PWM) depending on configuration.

The UARTs don’t exactly work like ACIAs. The hardware handshake control is actually controlled in software. The data sheet goes into a lot of detail regarding the UARTs and the source for the monitor rom is available on WDC’S website.

Cheers,
Andy

I thought I knew how to do all this, but then I read 265iromlist (cleaned up by Andrew Jacobs), which gives the code for the internal rom, and sheesh! Now I am utterly confused!

Jonathan

It was nice that WDC provides the source for the ‘265 monitor rom and reference manual. Out of the box the internal rom will start the ‘265 with virtually no resources only what ram, rom and I/O is on the chip. So while WDC ‘reserves’ some things for itself there’s no prohibition for writing your own rom for your own SBC for example. And that’s pretty much required if you want to use the PIB for whatever purpose you can imagine. You can put your own external boot rom in either of 3 places CS5B, CS4B or even CS3B and reclaim the port P4/P5 pins for the PIB’s use. I can’t speak for other retro computer platforms but the PIB seems to be made for interfacing the ‘265 with the Apple II/IIGS expansion bus.

Cheers,
Andy

Do you have a link for this clean version? I did a quick search but it was inconclusive. Thanks!