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PostPosted: Sat May 27, 2017 11:37 am 
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So besides RD & WR, Active high Reset, IACKN what other differences are there to consider?

I know that usually in a 68xxx system bus operations are synchronized with DTACK, however the datasheet states
Quote:
Systems not strictly requiring DACKN may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the bus cycle time.

And I'm pretty sure IACKN can just be tied high and ignored right?


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PostPosted: Sat May 27, 2017 3:38 pm 
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There was once a newsletter titled itself "DTACK GROUNDED" - just to indicate that they attempt to drive everything as fast as possible :)

So DACKN can be grounded. And if you don't need vector fetching IACKN = 1 should be OK. (I don't try to figure out how the timing of IACKN is (relative to VPB), the NXP datasheet puzzles me too much :?

On the other hand: you most probably have nWR and nRD for RAM/ROM access. So why not using 80xxx mode?


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PostPosted: Sat May 27, 2017 7:08 pm 
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LIV2 wrote:
So besides RD & WR, Active high Reset, IACKN what other differences are there to consider?

I know that usually in a 68xxx system bus operations are synchronized with DTACK, however the datasheet states
Quote:
Systems not strictly requiring DACKN may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the bus cycle time.

And I'm pretty sure IACKN can just be tied high and ignored right?

IACKN can be pulled up to Vcc and ignored, as the 28L92 timing doesn't have any special dependency on it.

As for as whether to use Intel or Motorola bus mode, my experience is that Intel mode is the way to go with the 65C816, as the 28L92's read and write operations are separately controlled. With the '816, I/O hardware must stay off the data bus (or be isolated with a bus transceiver) during Ø2 low in order to avoid contention when the '816 emits the bank bits. This is readily accomplished by gating the /RD and /WD signals with Ø2 high. Also, the 28L92 can be confused by the change of the data bus during a write cycle that occurs when Ø2 goes high, especially when accessing the command registers. Hence not asserting the WRN input on the 28L92 until Ø2 goes high is essential. In Motorola mode you don't have that control.

Either mode should be usable with a 65C02 machine, since the data bus behavior is less convoluted. Motorola mode will likely entail a little less glue logic.

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PostPosted: Sun May 28, 2017 5:47 am 
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Thanks!

I'm only playing with a 65C02 for now so I'm going to just use 68xxx mode, but I have a couple of Z80's to play with and probably will move on to the 65816 later so having support for both styles of bus is very handy


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PostPosted: Sun May 28, 2017 7:11 am 
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LIV2 wrote:
Thanks!

I'm only playing with a 65C02 for now so I'm going to just use 68xxx mode, but I have a couple of Z80's to play with and probably will move on to the 65816 later so having support for both styles of bus is very handy

Can't help you with the Z80—I know zip about that hardware. My use of the 28L92 has been with the 65C816.

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PostPosted: Sun May 28, 2017 10:55 am 
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I think I should point out that it's also fairly easy to adapt the Intel bus mode to the 65xx bus. In my opinion, easier than the 68K one.
I use one in my build, which is 65C02-based, and I didn't attempt to use the Motorola bus mode because I couldn't figure out what I needed to do to adapt it(not that I tried very hard). The Intel bus seemed easier to adapt, possibly because the RAM and ROM I'm using use something similar, so I already had most of the adaptor circuitry. All I had to do was implement the active-high reset.


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PostPosted: Sun May 28, 2017 11:51 am 
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I've been playing around with it in 68xxx mode and haven't had to adapt anything, other than the CS gated by PHI2 everything wires up directly to the bus.


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