litwr wrote:
It is possible to dream about the development of our beloved 6502 in the case that MOS Technology continued independently. Let's call these improved 6502 the 6502+. I can suggest the next steps which could keep 6502+ leadership up to the end of the 80s.
1) 1976 - the elimination of zp,X page warp. This step would allow the direct stack addressing.
Nice, but this usage would cost +1 cycle
- using abs+x (available) yield the same speed at the expence of one more program byte.
Adding an offs,S address mode would be more versatile IMHO.
litwr wrote:
2) 1977 - the elimination of empty cycles. This would make 6502+ 25% faster. This was done with 4510 but only in 1988. This step might also include the addition of several useful minor instructions like BIT#.
Oh yes, sadly lots of programs needs to be "adjusted" due to incorrect timing loops. And I'm sure, allthough it looks simple, it takes a huge amount of silicon to achieve this.
litwr wrote:
3) 1978 - the addition of the second accumulator. This would make 6502+ up to 100% faster.
Hmm, this is something I don't understand. Perhaps you can explain this dramatic speedup. But I assume adding 9 accumulators instaed of only one wouldn't yield +900% ??
litwr wrote:
4) 1979 - moving part of the zero page short addresses into registers. It might be 4 or 8 bytes, for example, starting at $80. The long (2 bytes) address to zp would be used for an access to zp RAM. This would increase 6502+ speed up to 50%.
Again I require additional explaination - you mean accessing $80 will use the internal "register", and accessing $0080 will use external RAM? So they could have different contents? If so, that means you are using
zeropage addressing as a flag to distinguish between external and internal memory. OK, then LDA ($80),Y will fetch two bytes (opcode and zpAddr) but then use reg80,reg81 add Y and finally fetch the data. Ideally this would take only 3 cycles instead of 5. In- or decrementing these "registers" would then again require 2 byte program data and ideally 2 cycles (more likely 3 cycles, since you have to fetch, change, and restore the register) saving 3 or 2 cycles.
Hee hee - if register <> memory you could fill a program into $0080++ and run it, using regs$80++ having a different contents. Nicely odd
litwr wrote:
5) 1980 - more zp to registers and the addition of byte by byte multiplication instruction like at 6809.
Yes, nice.
litwr wrote:
6) 1981 - the support for 16 MB memory addressing with the introduction of an mode register and an address mode bit in it. 6502+ would fetch 3 bytes for any address in 16 MB mode and 2 bytes in the old 64 KB mode.
...
IMHO this architecture would be faster than even mighty ARM or Intel 80486 at 1991.
Well, IMHO that's beyond the scope of 65xx.