Is possible to obtain the SYNC signal in processor that does not have it
MOS6510 ...

I think you have to build a little instruction decoder state machine - Jeff's territory really - which is then a little more complicated if you also have to deal with RDY.

Actually, I think you can give yourself a bit of an assist by also monitoring the address bus - otherwise you have to compute things like page crossing penalty cycles. And in a system with interrupts you'd also need to know the exact cycles in which interrupts are taken.

This is sounding complicated! Would it be enough to get it nearly right?

This is idea.
I think for example. On AVR microcontroller which followed the instructions to the CPU.
I would like to simulate the MOS 6509 on 6510.
Or maybe just enough to catch opcodes $ B1 / $ 91?
But how?
http://forum.6502.org/viewtopic.php?t=2023

That's an idea! Using a cycle-accurate simulation on a microcontroller is a lot more practical than building a 6502 in logic.

But for detecting just two specific opcodes which use (zp),Y addressing, it might not be too difficult to build a finite state machine which detects the two zero page accesses after seeing the specific opcode on the databus followed by an operand, and then counts cycles. Here's a trace:
http://visual6502.org/JSSim/expert.html ... eab122eaea

There are probably not very many ways of getting two consecutive accesses to zero page, other than it being the fetch of an operand for indirect addressing. Or jumping into zero page, but you could just say "don't do that!" Or you could say that a jump into zero page will be preceded by a read of 00 on the database, and ensure that isn't the case.

It's probably really hard.
If I had SYNC (or know when it ends the previous owner) I could recognize opcodes $ B1 / $ 91 and replace them on the fly and turn into BRK interrupt.

I wonder, why the 6509? Is it because you want to run software written for the CBM-II ? (The scheme used by the 6509 is flawed, IMO.)

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

That's right, I wanted to run a CBM-II system on my C64 with 16 MB of RAM.
http://forum.6502.org/viewtopic.php?f=4&t=2989

Alright, then -- 6509 simulation it is. And, the flaw I mentioned probably could be fixed without breaking compatibility.

I have to go now, but I will have more time to talk later.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It might be that a GODIL or similar FPGA board would substitute for the 6510, in which case you can put in a 6502 core and then it can be tweaked as necessary.

Or, maybe the idea is to arrange this trick by connecting only to the cartridge port?

I do quite like the idea of spotting the two special instructions by observing bus activity. The pattern to match is something like
1 - read, returning B1 or 91
2 - read from the following address, this is the operand, a zero page address
3 - read of that given zero page address
4 - read from the following address, being the high byte of the pointer
(At this point you commit to a banked data access, or two of them.)
5 - read of the (banked) destination address, supposing no overflow from the Y addition
6 - write (if it's a STA) of the (banked) destination address, or a read if it's a LDA and there was a page crossing, or a read of the (unbanked) next instruction if it was LDA without a page cross.

It's easy to pick off the STA case. The LDA case is tricky because you don't know if there will be a page crossing. You do know the value of PC though, so you can see from the address whether cycle 6 is an unbanked fetch or a banked read.

Edit: but note that with this approach you can't tell at the time of the initial fetch that it was a fetch, so you can't substitute the opcode with a BRK. You have to have banking hardware ready to switch in during cycles 5 and possibly 6.

This is a schema of the extension of RAM.
The addition of two registers 6509 is possible.

Hardware is ready swich bank during one cycle

I wish all processors had the SYNC signal! And I guess they all do, but only internally -- not brought out on a pin where we can use it as part of a circuit that changes how instructions work. The Motorola/Hitachi 6809/6309 cpus would be great to tinker with -- they need 16 MB, too!

Edit: The "E" variants -- 6809E and 6309E -- feature a signal called LIC, or Last Instruction Cycle. LIC differs somewhat from SYNC but it does reveal when the opcode fetch takes place.

For 6510, you guys have cited some good alternatives:

• use an FPGA cpu core to be the 6510, modified in regard to $91 & $B1 opcodes (which are used by 6509 programs for banked addressing)
• detect $91 & $B1 opcodes running on a real 6510 by simultaneously running a 6510 simulator on an AVR
• detect $91 & $B1 opcodes running on a real 6510 by watching R/W and signals on the buses

I just noticed a different challenge, though. The 6510 has an IO port and its data-direction register located at $0000 and $0001. But those same addresses are used by 6509 for the extended address registers! So, when running a 6509 program, you'd have to prevent its accesses to 0000 & 0001 from being "heard" by the 6510. And vice-versa would be awkward too. Thinking out loud, here...

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Another alternative (even though this is the hardware forum) would be software emulation via code analysis. Given that this is a very short-lived architecture, you could suppose that the software you'd run on it was well-behaved in terms of accessing the new hardware features. For instance, assume that $00/$01 access was all done by straight LDA/STA zp instructions, and detect those in the code stream.

If you do have 16MB, and are emulating a 1MB architecture, and are willing to give up timing accuracy (BRK substitution already does that), then you should have plenty of elbow room for tables & analysis. This is the sort of things that emulators on the PC do with JIT'ing chains of instructions, but in this case no JIT transformation is required because the instruction sets are compatible.

I think it would be more work than a hardware solution, but if the hardware solution isn't feasible it is an alternative.

_________________
WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

You could even use the 6502 and add registers as in 6509 and 6510.
Now, I think it would be the easiest.