Joined: Mon May 25, 2015 2:25 pm
Posts: 632
Location: Gillies, Ontario, Canada
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Thanks! I will be posting everything as a final project once the code is optimized and commented. Here is the code so far, without much optimizing and no sound routines... Code: //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// AVRCADE.COM - MINIMAL 6502 COMPUTER CHIPSET //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// TARGET : ATMEGA-1284 @ 25.175 MHZ ////////// VIDEO : 216 x 120 @ 16 COLORS ////////// AUDIO : TO BE COMPLETED ////////// HARDWARE AND CODING BY RADICAL BRAD ////////// VERSION DATE : DEC 28 2016 //////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// 25.175 MHZ TIMING FOR 640 X 480 @ 60 HZ VGA STANDARD //////////////////////////////////////////////////////////////////////////////////////////////////////// // HSP : 096 FROM 0000 TO // HBP : 048 FROM TO // HPX : 640 FROM TO // HFP : 016 FROM TO // TOT : 800 // VLN : 480 FROM 000 TO 479 // VFP : 011 FROM 480 TO 490 // VSP : 002 FROM 491 TO 492 // VBP : 032 FROM 493 TO 524 // TOT : 525 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// 6502 AND AVR MEMORY MAPPING AND USAGE //////////////////////////////////////////////////////////////////////////////////////////////////////// // 6502 ADDRESS SEGMENT SEGMENT SIZE SEGMENT DESCRIPTION AVR MEMORY MAPPED LOCATION // 00000 TO 00255 00256 BYTES ZERO PAGE RAM SRAM FROM 00256 TO 00511 // 00256 TO 00511 00256 BYTES HARDWARE STACK SRAM FROM 00512 TO 00767 // 00512 TO 13471 12960 BYTES VIDEO MEMORY SRAM FROM 00768 TO 13727 // 13472 TO 16371 02900 BYTES PROGRAM RAM SRAM FROM 13728 TO 16627 // 16372 TO 65529 49158 BYTES PROGRAM ROM FLASH MEMORY MAPPED // 65530 TO 65531 00002 BYTES NMI VECTOR FLASH MEMORY MAPPED // 65532 TO 65533 00002 BYTES RESET VECTOR FLASH MEMORY MAPPED // 65534 TO 65535 00002 BYTES BRK VECTOR FLASH MEMORY MAPPED //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// AVR DEDICATED REGISTERS //////////////////////////////////////////////////////////////////////////////////////////////////////// // R2 : CONSTANT ZERO VALUE // R3 : TEMP REGISTER TO SAVE DATA BUS // R6 : TEMP REGISTER TO SWAP XL // R7 : TEMP REGISTER TO SWAP XH // R8 : TEMP REGISTER TO SWAP XL // R9 : TEMP REGISTER TO SWAP XH // R24 : 6502 VALID ADDRESS LO BYTE // R25 : 6502 VALID ADDRESS HI BYTE // XL : VIDEO MEMORY POINTER LO BYTE // XH : VIDEO MEMORY POINTER HI BYTE // YL : VIDEO LINE COUNTER LO BYTE // YH : VIDEO LINE COUNTER HI BYTE // ZL : PROGRAM ROM POINTER LO BYTE // ZH : PROGRAM ROM POINTER HI BYTE //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// ATMEGA-1284 INITIALIZATION AND STARTUP //////////////////////////////////////////////////////////////////////////////////////////////////////// .global main main: // ATMEGA-1284 INCLUDES ABD DEFINES #include <avr/io.h> #define __SFR_OFFSET 0 // SETUP PORT A cbi DDRA,0; 6502 ADDRESS BIT 00 cbi DDRA,1; 6502 ADDRESS BIT 01 cbi DDRA,2; 6502 ADDRESS BIT 02 cbi DDRA,3; 6502 ADDRESS BIT 03 cbi DDRA,4; 6502 ADDRESS BIT 04 cbi DDRA,5; 6502 ADDRESS BIT 05 cbi DDRA,6; 6502 ADDRESS BIT 06 cbi DDRA,7; 6502 ADDRESS BIT 07 // SETUP PORT C cbi DDRC,0; 6502 ADDRESS BIT 08 / PIXEL DATA BIT 0 cbi DDRC,1; 6502 ADDRESS BIT 09 / PIXEL DATA BIT 1 cbi DDRC,2; 6502 ADDRESS BIT 10 / PIXEL DATA BIT 2 cbi DDRC,3; 6502 ADDRESS BIT 11 / PIXEL DATA BIT 3 cbi DDRC,4; 6502 ADDRESS BIT 12 / PIXEL DATA BIT 4 cbi DDRC,5; 6502 ADDRESS BIT 13 / PIXEL DATA BIT 5 cbi DDRC,6; 6502 ADDRESS BIT 14 / PIXEL DATA BIT 6 cbi DDRC,7; 6502 ADDRESS BIT 15 / PIXEL DATA BIT 7 // SETUP PORT B cbi DDRB,0; 6502 DATA BIT 0 cbi DDRB,1; 6502 DATA BIT 1 cbi DDRB,2; 6502 DATA BIT 2 cbi DDRB,3; 6502 DATA BIT 3 cbi DDRB,4; 6502 DATA BIT 4 cbi DDRB,5; 6502 DATA BIT 5 cbi DDRB,6; 6502 DATA BIT 6 cbi DDRB,7; 6502 DATA BIT 7 // SETUP PORT D sbi DDRD,0; HORIZONTAL SYNC sbi DDRD,1; VERTICAL SYNC sbi DDRD,2; VIDEO BLANKING sbi DDRD,3; AUDIO OUTPUT sbi DDRD,4; 6502 CK cbi DDRD,5; 6502 RW (LO:WRITE / HI:READ) sbi DDRD,6; 6502 BE (LO:TRISTATE / HI:ACTIVE) sbi DDRD,7; 6502 RS (LO:RESET / HI:RUN) // SET TIMER 1 VIDEO INTERRUPT ldi r16,(1<<CS10 | 1<<WGM12) sts TCCR1B,r16 // SET TIMER1 MATCH INTERRUPT ldi r16,(1<<OCIE1A) sts TIMSK1,r16 // SET TIMER1 INTERRUPT TIME ldi r16,hi8(800) sts OCR1AH,r16 ldi r16,lo8(800) sts OCR1AL,r16 // SET ALL PORTS LOW clr r16 out PORTA,r16 out PORTB,r16 out PORTC,r16 out PORTD,r16 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// 65C02 INITIALIZATION AND STARTUP //////////////////////////////////////////////////////////////////////////////////////////////////////// // ENABLE 6502 BUS sbi PORTD,6 // RESET 6502 cbi PORTD,7 // SEND CLOCK CYCLES clr r16 RSCLK: cbi PORTD,4 nop nop nop nop nop nop sbi PORTD,4 nop nop nop nop nop nop dec r16 brne RSCLK // UNRESET 6502 sbi PORTD,7 // RESET DELAY clr r16 RSDLY: inc r16 brne RSDLY //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// SYSTEM INITIALIZATION AND STARTUP //////////////////////////////////////////////////////////////////////////////////////////////////////// // CLEAR REGISTERS clr r2 ser r16 mov r14,r16 ldi XL,lo8(768) ldi XH,hi8(768) movw r6,X ldi XL,lo8(256) ldi XH,hi8(256) movw r10,X ldi ZL,lo8(ProgMEM) ldi ZH,hi8(ProgMEM) movw r12,Z // START VIDEO INTERRUPT sei //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// 65C02 CLOCK AND MEMORY ACCESS CONTROLLER //////////////////////////////////////////////////////////////////////////////////////////////////////// RUN6502: // 6502 CLOCK CYCLE cbi PORTD,4 sbi PORTD,4 // READ ADDRESS FROM 6502 in r24,PINA in r25,PINC // CHECK RW STATUS sbis PIND,5 rjmp WRITE6502 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// 6502 READ REQUEST : RW HI //////////////////////////////////////////////////////////////////////////////////////////////////////// // SET AVR DATA BUS FOR OUTPUT out DDRB,r14 // CHECK FOR RAM MEMORY cpi r24,lo8(16371) ; use movw ldi r16,hi8(16371) cpc r25,r16 brlo q1 // READ FROM ROM MEMORY movw Z,r12 ldi r16,hh8(ProgMEM) out RAMPZ,r16 add ZL,r24 adc ZH,r25 clr r16 brcc gg inc r16 gg: out RAMPZ,r16 elpm r16,Z rjmp q2 q1: // READ FROM RAM MEMORY movw X,r10 add XL,r24 adc XH,r25 ld r16,X q2: // SEND DATA TO 6502 out PORTB,r16 // SET AVR DATA BUS FOR INPUT out DDRB,r2 // END OF READ REQUEST rjmp RUN6502 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// 6502 WRITE REQUEST : RW LO //////////////////////////////////////////////////////////////////////////////////////////////////////// WRITE6502: // CHECK FOR RAM MEMORY cpi r24,lo8(16371) ; use movw ldi r16,hi8(16371) cpc r25,r16 brlo b1 // WRITE TO PIXEL X REGISTER cpi r24,lo8(32768) ldi r16,hi8(32768) cpc r25,r16 brne rr1 in r22,PINB rr1: // WRITE TO PIXEL Y REGISTER cpi r24,lo8(32769) ldi r16,hi8(32769) cpc r25,r16 brne rr2 in r23,PINB rr2: // WRITE TO PIXEL COLOR REGISTER cpi r24,lo8(32770) ldi r16,hi8(32770) cpc r25,r16 brne rr3 ldi XL,lo8(768) ldi XH,hi8(768) add XL,r22 adc XH,r2 ldi r16,108 mul r23,r16 add XL,r0 adc XH,r1 in r16,PINB st X,r16 rr3: // END OF GPU WRITE rjmp RUN6502 // SET POINTER TO RAM b1: movw X,r10 add XL,r24 adc XH,r25 // WRITE DATA TO MEMORY in r16,PINB st X,r16 // END OF WRITE REQUEST rjmp RUN6502 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// HORIZONTAL SYNC PULSE = 96 CYCLES //////////////////////////////////////////////////////////////////////////////////////////////////////// .global TIMER1_COMPA_vect TIMER1_COMPA_vect: // HORIZONTAL SYNC ON (2) cbi PORTD,0 ;2 ; SAVE REGISTERS (7) push r16 ;2 in r16,SREG ;1 push r16 ;2 movw r8,X ;1 movw X,r6 ;1 ; EQUALIZE INTERRUPT LATENCY (11) #define fix 17 lds r16,TCNT1L ;2 cpi r16,fix+0 ;1 brlo FIX0 ;1/2 FIX0: cpi r16,fix+1 ;1 brlo FIX1 ;1/2 FIX1: cpi r16,fix+2 ;1 brlo FIX2 ;1/2 FIX2: // VERTICAL SYNC FROM 492 TO 493 (16) ldi r16,hi8(492) ;1 cpi YL,lo8(492) ;1 cpc YH,r16 ;1 brne AVRC_HSL1 ;1/2 cbi PORTD,1 ;2 AVRC_HSL1: breq AVRC_HSL2 ;1/2 nop ;1 nop ;1 AVRC_HSL2: ldi r16,hi8(494) ;1 cpi YL,lo8(494) ;1 cpc YH,r16 ;1 brne AVRC_HSH1 ;1/2 sbi PORTD,1 ;2 AVRC_HSH1: breq AVRC_HSH2 ;1/2 nop ;1 nop ;1 AVRC_HSH2: // LINE COUNTER WRAP AT 525 (13) adiw YL,1 ;2 ldi r16,hi8(525) ;1 cpi YL,lo8(525) ;1 cpc YH,r16 ;1 brne AVRC_LWL ;1/2 clr YL ;1 AVRC_LWL: brne AVRC_LWH ;1/2 clr YH ;1 AVRC_LWH: brne AVRC_LCL ;1/2 ldi XL,lo8(768) ;1 AVRC_LCL: brne AVRC_LCH ;1/2 ldi XH,hi8(768) ;1 AVRC_LCH: // DELAY (48) ldi r16,1 qq1: dec r16 brne qq1 // DISABLE 6502 BUS cbi PORTD,6 // ENABLE VIDEO BUS ser r16 out DDRC,r16 // HORIZONTAL SYNC OFF (2) sbi PORTD,0 ;2 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// HORIZONTAL BACK PORCH = 40 CYCLES //////////////////////////////////////////////////////////////////////////////////////////////////////// // BLANKING FROM 480 TO 524 (5) ldi r16,hi8(480) ;1 cpi YL,lo8(480) ;1 cpc YH,r16 ;1 brcs AVRC_ACT ;1/2 rjmp AVRC_BLK ;2 AVRC_ACT: // SET VIDEO MEMORY LINE (7) mov r16,YL ;1 andi r16,3 ;1 cpi r16,0 ;1 breq AVRC_SV1 ;1/2 subi XL,108 ;1 AVRC_SV1: breq AVRC_SV2 ;1/2 sbc XH,r2 ;1 AVRC_SV2: // ENABLE PIXELS (3) out PORTC,r2; 1 cbi PORTD,2 ;2 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// HORIZONTAL PIXEL LINE = 648 / 3 = 216 PIXELS / 8 = 27 CHARACTERS //////////////////////////////////////////////////////////////////////////////////////////////////////// ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 ld r16,X+ ;2 out PORTC,r16 ;1 swap r16 ;1 nop ;1 out PORTC,r16 ;1 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// ////////// HORIZONTAL FRONT PORCH = 16 CYCLES //////////////////////////////////////////////////////////////////////////////////////////////////////// AVRC_HFP: // HORIZONTAL BLANKING (4) nop; 1 nop ;1 sbi PORTD,2 ;2 AVRC_BLK: // DISABLE VIDEO BUS out DDRC,r2 // ENABLE 6502 BUS sbi PORTD,6 // restore data //out PORTB,r3 // RESTORE REGISTERS (7) movw r6,X ;1 movw X,r8 ;1 pop r16 ;2 out SREG,r16 ;1 pop r16 ;2 ; RETURN FROM INTERRUPT reti ;4 //////////////////////////////////////////////////////////////////////////////////////////////////////// ////////// ////////// INCLUDE 6502 ASSEMBLED 64K BINARY IMAGE //////////////////////////////////////////////////////////////////////////////////////////////////////// #include "6502MEM.s" I am going to clean this up, add some sound, and then do a basic 6502 demo program. The memory arbiter ate a LOT of cycles, so this isn't the fastest thing I have ever made. Should just barely outperform a C64 for graphics speed. Sound will be about as good as a VIC20. Cheers, Brad BigEd wrote: Interesting project Brad, and impressive results with the video from the AVR. Did you share your code, or do you intend to?
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