Sorry for the stream of weird questions today...you wouldn't believe how much sleep I loose because these topics occupy my thoughts and I sometimes have to get them out in the open.

Anyway, while studying CPLD's and the Apple II video generation, I started wondering how the 65C816 would handle this in the context of >64K of RAM.

For example, the video generators of the Apple II would access RAM during the low phase of PHI2, store in a latch and send to the screen. During the high phase, the CPU would access the RAM. Beautiful design.

Now, it is my understanding that the '816 gains an extra 8 bits of address space by multiplexing the databus during the low phase of PHI2. Forgive me if I'm wrong on that...that's what I understand.

If this is the case, how would a similar video generator access the RAM during that same phase if the data bus is, essentially, setting address pins A23:16 at the same time?

I'm reading the datasheet for the '816...so maybe I'm missing something silly.

Thanks for any insight!

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Cat; the other white meat.

I think the answer is that the databus coming from the CPU is not the same as the databus feeding the RAM - there's at least some kind of tristate buffer or mux between the two. In phi1, the CPU's databus feeds a latch, but not the RAM. The RAM's databus is connected to the video system. In phi2, the buffer is turned on and the CPU and RAM are connected.

Sorry to bring up my old topic but I've been thinking about this again. I want to make sure I understand what you're saying.

Let's say I want an FPGA to arbitrarily jump to any 24 bit address in RAM during PHI1 while the CPU is doing its thing.

So, during PHI1 (low) the CPU's databus feeds a latch. Which is temporarily holding on to "virtual" address pins A16 to A23. The real address pins from the CPU (A0 - A15) are connected to RAM as usual.

During this phase, how would the video system "take over" the RAM and change all 24 bits if the CPU's 16 bits of address pins are tied to the RAM? Would I latch the entire 24 bit address bus during this time and when we enter PHI2, connect the 24 bit latches to the RAM?

So basically the CPU would never set the RAM address directly. It would always latch the 24 bit address temporarily. Meaning the entire databus and address bus would need to be tristated so the FPGA could take over during PH2.

Am I understanding that correctly or is there an easier way?

Thanks!

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Cat; the other white meat.

All address lines of the video RAM are switched between video address generator (your FPGA etc.) during PHI1 and the 816 during PHI2. The data lines of the video RAM are switched as well: during PHI2 they are connected to the 816 while during PHI1 there output wents to some shift registers etc. generating the (serial) video stream. If present (or realized within the FPGA) a video processor could write data into the RAM during PHI1 as well (probably during the horizontal and vertical blank periods).

Hope this helps.

Perhaps a bit more precisely:

The address lines are unidirectional.
They come from the VAG (video address generator or refresh address generator) to read the video content out of your video RAM. They are active during PHI1.
During PHI2 the addresses come from the CPUs address bus. The CPU places the information that is to be displayed into the RAM during this period.
To switch between VAG addresses and CPU addresses a multiplexor can be used. But it is also possible to use bus drivers and their output enable controls.

The data lines are used only for a fraction of either PHI1 or PHI2 and therefor bidirectional bus drivers with tristate control (e.g. LS245) are a common solution to separate the data buses. If the VAG is only used to generate refresh addresses then only one LS245 o.e. is required to isolate the CPU data bus from the video data bus.

Perhaps you may take a look to the 6545 data sheet and application note in the document section of the forum. The 6545 is a simple VAG and there are various strategies shown how to connect video RAM.


Regards

My SBC-3 used a 65816 with 512K of RAM and a CPLD was used to drive a composite color display using the PHI2 low phase for video and PHI2 high for the CPU. It worked quite well. I even used the same video address counters to fill RAM addresses $08000-$0FFFF from an EEPROM during RESET. The slower EEPROM was then put in low power standby while the system ran from the faster RAM.

here's a block diagram:


More info on the system can be found here:
http://sbc.rictor.org/info3.html

Let me know if I can help explain anything about that board.

Daryl

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Please visit my website -> https://sbc.rictor.org/