> I'm resetting the 6850 by writing the master reset to the control
> register and then immediately writing the regular control word to it. E is
> driven by phase-2, and the chip enable is driven during the entire read
> cycle. When I read the status register, I get low levels for D0-D5, but
> D6 is high during the first half of the cycle, while D7 is high during the
> second half. It's really strange.
You may have already checked these, but here it is anyway. It may benefit someone else.
By "the first half of the cycle," I assume you mean when phase 2 is down. If so, perhaps there's a glue logic error because, with a few execptions that don't usually exist in small home-made computer boards, nothing should be putting data on the data bus during that time. Everything should be high-impedance, and the parasitic capacitances should just hold the last logic states from when phase 2 was up. The R/W\ , register selects, and chip selects have to be valid a minimum amount of time before the E (phase 2) goes up. Is it possible a couple of pins got crossed in the wire-wrapping? Is there a good reason Status<7> (interrupt occurrence bit) is already set? According to the data book, it doesn't look possible to have bit 7 is set while bits 0 through 6 are clear, which is another reason to suspect a wiring error. Otherwise, are you sure the IC is good? Does it work in another circuit? If it could have been damaged with static, do you have another one to try to see if it behaves the same in your circuit? When you read out high and low levels, are the voltages reaching close to 0 and +5V? (In-between levels could indicate bus contention or that a power or ground pin someplace didn't get connected.)
> Anybody with any experience with the 6850 have any ideas?
> I'd appreciate some help!
No 6850 experience here, just a Mot data book and 65xx and other experience. Why not use the 6551 with the on-board crystal oscillator and baud rate generator?
Garth
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