The MOnSter 6502 - a transistor-level recreation on one PCB.

[BigEd]

Just posted on the mos6502 g+ page:

Quote:

Breaking news! Eric Schlaepfer has just broken cover with his MOnSter 6502 project - using quad MOSFET surface mount transistors he was able to duplicate exactly the NMOS 6502 netlist as used in the simulator at visual6502.org - by using MOSFETs he avoided the pitfall of most low-level recreation attempts, which is coping with the bidirectional switches between the internal busses.



The starting point was to calculate the size of PCB - on estimating that it might be about a square foot, the project was on. There's more project timeline in the blog at
http://tubetime.us/?p=346
and a discussion on Hacker News at
https://news.ycombinator.com/item?id=11703596

Hat tip to +Kam-Yung Soh and +Samuel Falvo II

(We normally post weekly but this is a special occasion!)

[pnoyes]

That is really cool!

I am going to the Maker Faire so I get to see it this weekend!

[BigEd]

Do let us know what you find!

[ElEctric_EyE]

Fascinating! What is the max speed of the macro die?

[BigEd]

Oops, I should have linked to the main project site: http://monster6502.com/ where you'll see
"The maximum reliable clock rate is not yet determined, but we expect it to be in the tens to hundreds of kilohertz range."

Also noteworthy: the foot-square PCB took ten weeks to route, by hand.

[Martin_H]

That's amazing. Thanks for posting it.

[cbmeeks]

But can it run Quake?

LOL, just kidding....that's amazing.

[Dr Jefyll]

This is a remarkable project! Congratulations are in order for Eric Schlaepfer and Evil Mad Scientist Laboratories.

On a related topic, now is a good time to remember that 6502.org's own ttlworks is also the maker of a discrete-transistor CPU, although his MT15 is not a 6502 replica. Links to more photos can be found here. And his Technical Articles Folder has more on his custom CPU's, including the 3000-transistor MT15.

-- Jeff

[ttlworks]

Jeff, thanks for mentioning MT15.

Gate capacitance of nowadays MOSFETs still is a bit too high, that's the problem.

For instance, if one wants just to build a single CMOS inverter with logic level MOSFETs,
making it faster than 3MHz probably would drain > 30mA from a 5V power supply.

So bipolar transistors like BC847\BC857 seem to be a much better choice
when trying to build a transistor CPU...

Unfortunately, the 6502 architecture deliberately aims at FET transistors,
transfer switches and such.

And without understanding the NMOS 6502 down to the smallest little detail,
starting a redesign for being able to build an implementation based on
bipolar transistors won't have much chance of success.

That's why I haven't tried to build something like a transistorized 6502.


MOnSter 6502 certainly is an amazing and fascinating project,
congratulations to Eric Schlaepfer and Evil Mad Scientist Laboratories !


A 4 layer PCB of that size sure isn't cheap, and as a designer you can't exactly say
if the prototype would be working at all until you are through with soldering
thousands of tiny SMD parts.

BTW:
Since PCB prices go down pretty much when ordering a lot of identical PCBs,
MT15 was a bitslice design. One Bit per PCB...

What had limited the speed in MT15 was, that the inverters showed a hysteresis
to the input signal which increased when frequency increased,
but unfortunately I wasn't aware about this effect from the start.

[BigEd]

(Great PLA ttlworks!)

[ttlworks]

Thanks, BigEd.

The "traditional" approach to building a PLA would have been a diode matrix ROM.

Unfortunately, you can't just build large diode matrix ROMs,
current and capacitance puts a limit to that.

Back then, BC847\BC857 SMD transistors were in the same price range as 1N4148 SMD diodes
(while having a smaller package).
And unlike diodes, transistors do current gain...

So when building the MT15 PLAs, I had decided to go for CTL instead,
"complementary transistor logic".

Basically, CTL is sort of an "outgrow" of ECL emitter dotting.

For instance, a two input CTL AND gate built with BC847\BC857 feeding a 330 Ohm load
could have a propagation delay of less than 5ns because the transistors just are
"clamping" a voltage without working as a saturating switch.

Outputs of CTL AND gates can be wired_ORed together and tied to one single
pull_down resistor to form AND\OR combination gates,
did this with the outputs of two PLA PCBs.

I wasn't sure if CTL would be working as intended... but it did.

http://6502.org/users/dieter/mt15b/mt15b_1.htm


BTW: just in case that somebody might try to build a bipolar transistorized 6502,
my advice would be to go for a 3.3V power supply, to make massive use of CTL,
and to build inverters with BSV52 transistors (Schottky clamped with a LL101).
Adding a resistor (some kOhm) in parallel to the LL101 seems to fix that
little hysteresis problem I had mentioned... although I have no idea, why.

[Drass]

Amazing projects! It's fascinating to get a glimpse of the issues and tradeoffs at this level - quite a high-wire act! Thanks for sharing these details.

[ttlworks]

Scary thing is, that successfully completing projects of that sort
just might give you a glimpse about the problems you might bump into
when trying to design your own chip...

...not to mention that a square inch of processed silicon sure is more
expensive than a square inch of processed PCB material.


When MOS had introduced the 6502 at the incredibly low price of $25
(CPUs from the competition were a lot more expensive back then),
we could assume that the designers at MOS had to pull quite a few tricks
related to logic design, optimisation, making the chip layout,
the manufacturing process etc.

So in my opinion, the whole NMOS 6502 is just one big "hardware hack",
and the result of a long optimisation process.


Clear text:
I think that trying to reconstruct the original concepts and ideas
of the designers out of the transistor level NMOS 6502 schematics
might be about as much fun as trying to reconstruct a cow from a
truckload of burgers.

Unfortunately, when trying to build a transistor level implementation
of the 6502 running at a reasonable speed (at least at 1 MHz that is)
with nowadays transistors, there only seem to be two choices:

To go through this adventure, or to come up with your own architecture.

Looking forward to see some some more projects like MOnSter 6502.

Best wishes and congratulations to Eric Schlaepfer and Evil Mad Scientist Laboratories.
Looking forward to see what they may create in their next project...

[pnoyes]

If you want to see another crazy project in the works:

https://hackaday.io/project/11677-the-diode-clock

This guy intends to build a CPU out of nothing but diodes.

[BigEd]

Here's Eric Schaepfler walking through a demo of the Monster 6502:
https://www.youtube.com/watch?v=73h4cjTeX44

via the article at http://makezine.com/2016/05/27/this-fun ... microchip/