Every 6502 system needs some kind of
memory decode, and there are several options with various tradeoffs. If I can, I'd like to summarise some options here, with links where possible - please comment so I can update this post with the best information. (I won't get into choosing among the several 74 series families, it's
covered elsewhere.)
- Very few TTL gates like
Garth's 3-gate single chip decode which splits memory into four 16k blocks - I/O devices can each decode a single address bit so you can have up to 10 devices in the 16k I/O block, if each has a CS and a \CS pin.
- The obvious but slowish 3-to-8 decoder 74*138 divides memory into 8 blocks of 8k, two of them cascaded gives finer granularity but double the propagation delay. Or the 4-to-16 decode 74*154 for a finer split.
- A magnitude comparator like the 4-bit 74*85 or 8-bit 74*688 or 74*521. [Is this preferable to a 138 in some ways?]
- preprogrammed logic such as PAL or GAL (e.g.
Daryl's standard part gives one page of I/O, nearly 32k of RAM and a full 32k of ROM. Edit: Daryl also offers custom configurations - see
below.)
- your own PAL or GAL, for similar granularity but however you want it, once you've got the capability to program such a device.
- programmable logic such as CPLD or FPGA for pretty much any scheme you care to code, once you've set up the tools and the programming dongle.
(In all cases, add a latch or VIA to add banking. I think that's probably another topic.)