From p.36 of the
data sheet:
3.9 Reset (RESB)
Reset clears all internal registers (except T1 and T2 counters and latches, and the SR. In the RESB
condition, all pins are placed in the input state and bus holding devices maintain initial level if not driven.
The initial level can be Logic 1 or Logic 0 and are not initialized by on chip circuitry. Also, T1 and T2, SR
and the interrupt logic are disabled from operation. [...]
Quote:
Code:
lda VIA0_ACR
ora #%00001100 // ACR[4:2] = 011 - CB2 under external clock
sta VIA0_ACR
To be sure you'll get mode 011 (particularly if you're setting it up after having used another mode since reset), you'll also need to AND-out bit 4 (since the ORA won't force it to a 0).
Unfortunately, SR mode 011 has the one and only bug in the VIA, all brands. I tell about it in tip #8 of the "Tip of the Day" column, at
viewtopic.php?p=2310#p2310 . See also the section "Using the 6522's shift register for tons of input bits"
http://wilsonminesco.com/6502primer/pot ... l#22_SR_IN in the "circuit potpourri" page of the 6502 primer.
You should generally activate the interrupt capability
after setting up whatever it is that will do the interrupting though.