My First 65C02 Project: CHIP-8 Emulator [WIP]

[DavidBuchanan]

This is my first time designing and building a SBC. I originally intended to build this project over the Summer so that I could mention it in my university application, but I didn't have the time to actually start construction up until recently.

My eventual goal for this project is to write a CHIP-8 emulator that can play games on a 128x64 graphical LCD.

Currently, the hardware consists of:
- R65C02P4 CPU
- 128K SRAM (32K addressable)
- 128K EEPROM (16K addressable)
- R65C22P4 VIA
- MC86B50 UART

This is the current state of the project: (sorry for poor image quality)

So far I have the ROM, RAM, VIA and a 20x4 character LCD working. At first, I spent ages trying to diagnose a hardware issue, but It turned out to be just a software error - I had my address byte-order wrong! The clock signal is currently being generated by an arduino, but only because I'm waiting for an oscillator to be delivered. Since WW sockets are fairly hard to come by, I decided to solder SIL headers to the front of the PCB instead, which seems to be working fine so far. You may have noticed sockets for a ZX Spectrum keyboard, which I hope to wire up soon. When the project is finished, I'll probably house it inside the Spectrum's case, although I might 3D print one.

I have a couple of questions:
- Despite what the datasheet says, is the 68B50 likely to run off a 4MHz clock if I put it in ÷16 mode?
- Is implementing memory paging as simple as connecting the spare address lines to an output port on the VIA?

Also, I would like to thank Garth Wilson for his excellent 6502 primer, which I probably wouldn't have managed without.

P.S. Should I have put this in the Newbies' section?

[barrym95838]

DavidBuchanan wrote:

This is my first time designing and building a SBC. I originally attended to build this project over the Summer so that I could mention it on my personal statement, but I didn't have the time to actually start construction up until recently.

Congratulations!

Quote:

- Is implementing memory paging as simple as connecting the spare address lines to an output port on the VIA?

It certainly depends on what you mean by "memory paging", because there are varying levels of sophistication. You're going to want to make some careful decisions about where in your memory map you want to page. For manual paging, the simplest method would be to limit it to a portion, like $4000 to $7fff ... that way, you wouldn't have to worry about losing and/or having to carefully maintain your zero and stack pages, or your ROM vectors. For demand paging, you would almost certainly need a lot more hardware assistance than a VIA, but the details have been lost in my foggy college memories from a few decades ago.

Quote:

Also, I would like to thank Garth Wilson for his excellent 6502 primer, which I probably wouldn't have managed without.

Garth is awesome.

Mike B.

[DavidBuchanan]

Minor update:

The character LCD is now wired directly to the data bus, and I have added the graphical LCD:

[GARTHWILSON]

Thankyou for the compliments. There's more I would like to write about (and plenty of other things I would like to see others write about regarding the 6502 & '816 which I myself am definitely not qualified to), but I should to get back to building for a while before I take on any new writing projects. They always turn out to be a lot more work than I anticipated.

To add to what Mike said about doing banking by just adding some address lines via a VIA: If the banked range is just for data, it will probably be easier. If you have program material in other banks, going from bank to bank within that banked-memory window—say that window is address range $4000 to $7FFF like Mike's example—will require some sort of tricks like what Jeff is famous for. Otherwise, you would need to jump back to main memory, change the bank bits, then jump back into the bank window of $4000-7FFF. (Jeff or someone can set me straight if I'm forgetting something.) Changing the bank bits while you're in that window and making it work would range somewhere between difficult and impossible.

[BigDumbDinosaur]

GARTHWILSON wrote:

Changing the bank bits while you're in that window and making it work would range somewhere between difficult and impossible.

...which is why the 65C816 exists.

[DavidBuchanan]

Thanks for the paging advice. To be honest, at this point I have no need for memory paging, because I can't think of any programs to write that would need more than 32k. I also plan to implement SD card storage at some point, so I don't think I'll ever run out of ROM space.

One untested idea that I just had was to use paging for simple multitasking - each task has its own page (and therefore its own stack), and the pages are switched out on a timer interrupt.

[GARTHWILSON]

DavidBuchanan wrote:

Thanks for the paging advice. To be honest, at this point I have no need for memory paging, because I can't think of any programs to write that would need more than 32k.

I can think of many, many uses for a huge data space though. 32KB is an awful lot to fill with program.

Quote:

One untested idea that I just had was to use paging for simple multitasking - each task has its own page (and therefore its own stack), and the pages are switched out on a timer interrupt.

I have an article on simple methods for multitasking without a multitasking OS, for systems that lack the resources to implement a multitasking OS, or where hard realtime requirements would rule one out anyway, at http://wilsonminesco.com/multitask/ . The "Stacks potpourri" page and a couple of the other pages of the stacks treatise address matters relevant to multitasking as well.

Although each task may want its own hardware stack and ZP space, you'll probably also want some ZP space that's common to all tasks.