Hi All

I've been reading and learning from 6502.org for a while - great site, and it gave me the information I needed to start my own project.

But I hope the gurus here can help me with a problem I have been grappling with for several days now.

I am building a homebrew computer based on a w65c02s (see https://hackaday.io/project/5789-6502-homebrew-computer).
Currently it is working in the following configuration:
- CPU : w65c02s
- RAM : HM628128 SRAM
- EEPROM : w27c512
- IO : 2 x MOS 2625 PIA
- VDP : TMS9918
- Serial : CMD65sc51
- Sound : AY-3-8910

I am decoding the address space through a 74HCT138 which basically gives me the /CS signal I need. All timing is from a master 21.477MHz clock, divided down to 10.7MHz for the VDP, and 2.68MHz for the rest of the system (except the AY-3 which operates at 1.34MHz).

All was well with this, until I recently found that the 6526 can't keep up reliably at 2.68MHz, but works fine at 1.34MHz - not a massive surprise I guess as it normally operates around 1MHz in a C64, so I was seriously overclocking it.

So I bought a few w65c22s VIAs from ebay and plugged a couple in. The pinout is very similar to the 6526, but this is what I have done to wire up:
- CS1 is tied direct to +5V
- PHI2 is fed from the clock divider as for all other PHI2 signals
- /CS2 is wired to the appropriate 74HCT138 line
- R/W is fed from the CPU R/W
- /IRQ I have left unconnected for the moment (but will wire-OR it using a diode to the /IRQ of the CPU)
- D0-7 is wired back to the CPU data bus
- RS0-3 is wired back to the CPU A0-A3 address bus

I thought this should work fine - but I am getting absolutely zilch. I am using a simple monitor program to constantly read back from register 0 (or any register from 0x0 to 0xf) and it always comes back 0xB2 (which happens to be the high byte of the address the VIA maps to - 0xB200). If I plug the 6526 back in without any other changes to wiring, I get something sensible back.

I have tried putting pull-ups on various control lines (/CS, CS1 being the only ones that made sense) - but nothing. The return value of 0xB2 is what I get if nothing is plugged in to that IO address space (e.g. if the 6526 is plugged in, I get data back - but taking it out completely, I get 0xB2). So it is as if the w65c22 is completely unresponsive. I've tried other VIAs (I had a batch of 5) - all the same. I even tried a Rockwell R6522 - that also does nothing.

I can't understand why this doesn't work. Although I am using a mix of CMOS and NMOS parts, the CPU is driving the address and data bus and that is CMOS. The /CS decoder is a CMOS part too. And the clock is also a CMOS part.

So I must be doing something incredibly stupid - I hope someone can point out my schoolboy error!

Thanks in advance, Dolo

If PHI2 were missing or in some way incorrect then a 6522 could respond as you describe. But PHI2 is a signal that the 6525 doesn't use -- it has no PHI2 input, and doesn't require that signal to be appropriate.

I would look more closely at what's going on with PHI2.

EDIT:Come to think of it, a 6525 will work when its Chip-Select signal arrives partway through the cycle. But a 6522 requires CS to be valid before the rise of PHI2.

Is PHI2 one of the inputs that enables your 74HCT138? For 6522 that's not appropriate.

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Did you wire the /RESET line on the 65C22? Also, do you have some code that is initializing the chip?

_________________
Regards, KM
https://github.com/floobydust

Hi Jeff

I'm using a 6526 which does have Phi2. However, yes I just noticed comparing the 6526 and 6522 timing diagram that /CS needs to activate before Phi2 rise - so that's a schoolboy error indeed.

My decode logic does use Phi2 as an input, so that will be a reason it doesn't work. Damn - all was dandy until this point in time. I'm going to have to rip out the Phi2 input for my decoding - will try that.

This looks promising. I knew that I was too close to this - and hoped that an external pair of eyes could find something obvious.

Will let you know how this turns out - great input, and thanks for the fast reply.

Cheers, Dolo

Jeff - thanks for your help.

My decoding logic has been working for ages. But fundamentally it did use Phi2 to decide which select line to activate - and this is used for ROM, RAM and ultimately the 138 decoder for the IO space.

This was fine for part I was using there CS was active after Phi2 went high - but the 6522 (and 6551 I think), as you have indicated need /CS to be active before Phi2 high.

At first I thought this was going to require some significant recoding of my logic. However, I decided to just connect my Phi2 input to the decoder to +5V. A bit of a stab, but I figured that if I don't need to care about Phi2 during decode, then I will just eliminate the input by setting to 1 all the time.

Guess what - works first time, perfectly.

I can't thank you enough Jeff. I don't think I would have spotted this change in the timing for /CS - I was starting to think about going back to the 6526 and running the board at 1.34Mhz - which I was really feeling miffed at having to do.

I will put up some pictures etc. - although most of my on-going ramblings (and pics) are on this site: https://hackaday.io/project/5789-6502-homebrew-computer

Cheers, Dolo

Oops, sorry -- my day is just starting, and I haven't had my second cup of coffee yet!

Not sure I agree. I find timing diagrams tend to look the way you expect them to look. It's a very terse medium, and anything unexpected can be easy to overlook.

Want a quick & dirty fix? Maybe this idea is obvious. Solder another '138 on top of the one that's already there. From the top '138 run a flying lead from the output that's for driving the 6522 but leave the other outputs unconnected. Tie the +5 and GND to the '138 underneath; also all the inputs -- except the one that brings in PHI2 -- tie that one high.

Oops again! Didn't notice you had posted while I was typing. Glad things are working now.

Looking forward to hearing more about your project!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The Ø2 clock should never be used in RAM, ROM or I/O decoding. The 65C02 makes the address bus valid approximately midway through the Ø2 low phase, and maintains the address bus until after the fall of Ø2. There is a short period of time during Ø2 low when the address bus is invalid (i.e., changing) but is usually of no consequence to most hardware. Hence your chip selects should be made on the basis of what is on A0-A15, which will give the selected device the maximum amount of time available to respond to selection.

Similarly, the 65C816 makes the address bus valid about midway through Ø2 low. However, the address bus is not valid during some cycles in some instructions, primarily when indexing is being internally processed. The 65C816's VDA and VPA outputs tell you when the address bus is valid and should be used to qualify chip selects.

What should be qualified by Ø2 are reads and writes on non-65xx devices. Especially worth noting is that during a write cycle the data bus is valid only when Ø2 is high. Writing to a device when Ø2 is low may produce unexpected results, as the content of D0-D7 may be random in nature.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hi BDD (!)

I can't believe I had it so wrong for so long - and in the meantime my computer seemed to be working fine.

So digging around in my recollection, I think it was because my very first baby steps in breadboarding a 6502 were based on some stuff I had read on the www. I believe one of the very simple decoding schemes used Phi2 for ROM/RAM selection, so I just let that stick in my own thinking all this time. When I wanted to build something more substantial (my current project) and was thinking about the decoding, by default I just continued with using the Phi2 theme.

The decoding logic took me a while to get my head around, so when Jeff pointed towards my problem, I thought heck, this is going to take some undoing. Thank goodness that a simple tie to +5V of what was the Phi2 input to my decoding logic was all I needed to do.

Thanks for the advice - it's crazy I managed to get this far with such a fundamental error in my design!!

So, what this means is that I have two full speed 65c22 VIAs (by full speed, I mean 2.68MHz - at this speed the 6526 couldn't keep up reliably).

I already started to think if I could go faster - but the CMD 65c51 can't keep up at 5.7MHz. I have WDC parts (the 'N' model) - however this has a defect on the transmit data ready register, so will need to update my software to try this out.

Maybe I will continue to put some meat on the bones of the software first - I've written everything from scratch including keyboard handler (for to use BBC Micro hardware), SD Card driver, FAT16 handler).

I am sure I'll be coming back for more advice and corrections! But in the meantime, many, many thanks to the replies to my question today. Saved a lot of time and hair pulling!

Cheers, Dolo

> The 65C02 makes the address bus valid approximately midway through the Ø2 low phase
That's only true at some speed, for coincidental reasons - I don't think it's a very good way to think about the timing. What's really happening is that the address bus becomes valid (in the worst case) some little time after the fall of phi2. Which is to say, it's not instant, and it's generally going to be before the midway point of the cycle in most systems you'd see. But the time at which it happens has nothing to do with the rising edge of phi2.

As you know, Jeff put together some really useful animations and explanations.
http://laughtonelectronics.com/Arcana/V ... iming.html

The matter of selects involving phase 2 was addressed on this forum page: viewtopic.php?f=4&t=2660&start=15

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Jeff Laughton (Dr. Jeffyl) posted a page on his site that goes over the 65C02's timing in some detail, complete with some animated illustrations. It's worth studying, especially the discussion on what happens when the Ø2 clock waveform is asymmetric.


Yes, the "stuck" TxD ready bit in the WDC 65C51 is annoying. The required software kludge makes the transmit side of the driver less efficient than it could be.

I make no bones about the fact that I think the 65C51 (and its NMOS ancestor) is a junky design, and not just because of the TxD erratum. There are much better UARTs available. I have used the NXP (Phillips) SCC26C92 and SCC28L92 dual-channel UARTs in 65xx designs, as have several other members. André Fachat has successfully integrated a 16550 UART into his 65C02 machine. There are also SPI designs that perform well, such as the devices produced by Maxim. My soon-to-be-built POC V2 unit will use an NXP 28C94 four-channel UART.

So you do have options when it comes to UARTs.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I used the word "midway" to more-or-less describe the worst case situation, which is running Ø2 at the maximum allowable rate. As always, consultation of the timing diagram is essential if making a quest for maximum performance.


I mentioned that in a subsequent post.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Very enlightening folks. Humbled by and very grateful for the incredible knowledge on here. I spent ages on Garth's site learning - although clearly the nuance around decoding is something I hadn't absorbed properly.

I was looking to implement a memory map which allowed more than 32KB of RAM that Garth shows on his site. I ended up with the following (I've corrected the Phi2 issue):
44K Ram [c000 – ffff]
16K ROM [b000 – bfff]
4K IO Block [0000 – afff]
IO area multiplexed through a '138 to provide up to 8 0.5K IO blocks.

I will post the decoding logic at some point - although it is on the hackaday site too. I tried to put it here, but it looks a mess as the message editor doesn't preserve whitespace (I tried tab and actual spaces to get alignment, but to no avail).

Basically:
ROM = f & e
IO = f & ~e & d & c
RAM = ~ROM & ~IO (& Phi2)
(where f, e, d, c refer to the 6502 address lines A15-A12)

Enable lines for ROM, IO Decoder, RAM
27C512 EEPROM : /CE, /OE
74xx138 Decoder : /E1, /E2, E3
628128 RAM : /CS1, CS2, /WE

So I dusted off my Boolean algebra and converted to NAND and NOT gates (I only have 74xx00 and 74xx04 to hand) - I can't show it here as seems impossible to create a nice tabular format, but the details are on my hackaday space.

My decoding scheme uses two 74xx00 and one 74xx04. Seems to work, especially so now that the Phi2 issue is removed. Would be nice to compress the IO block to an even smaller space - 0.5K per device is unnecessary, most peripheral devices have 16 or fewer addressable registers. But when I looked at squeezing more addressable RAM, I felt the decoding was going to get even more cumbersome and I did also note Garth's warning about gate delays. The set up above has up to 3 gates of decode, which is quite a lot, so decided not to make it even more complex.

Cheers, Dolo

Again, if you're using 65-family I/O ICs, you can use the fact that these each have two chip-select inputs to your advantage, and eliminate the '138. Connect the CS\ of all of them to the I/O select line of your address decoding, and put the CS (positive logic) of individual ones to individual address lines. You'll save board space and propagation-delay time and a little work too.


These phpBB forums all work the same in that regard. Put [code] and [/code] around your code, and it will force monospacing and preserve the whitespace. The more user-friendly way in terms of learning is to mark your block and use the clickable things just above the box you're typing in to get the desired effect.


Be sure to see the propagation delays (in nanoseconds) of the individual parts in their data sheets, and add them up.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks Garth. The current address decoding scheme works fine, but yes I can see how I could eliminate the '138 with your approach. It doesn't compress the IO block unfortunately (I need to keep 4 bits for register addressing, and then 8 for device selection, plus the top 4 bits are needed to select the IO block) - but it would be quicker.

I don't only have 65-family ICs - video is generated by a TMS9918 VDP which is mapped to the IO address space. The TMS VDP has /CSR and /CSW lines - basically a combined /CS and R/W. Even so, this also doesn't need the '138 using the approach you describe.

Great spot, thanks! I may re-write the decoding around this scheme - but will put that in my priority B category as I have a few other things (more on the software side) to develop.