BigEd wrote:
Well done... that's an interesting little wrinkle in the 65C02's instruction set.
I note that
http://www.llx.com/~nparker/a2/opcodes.html describes 7C as JMP (abs,X) rather than JMP (ind,X)
Noted, thanks. I should really use the correct nomenclature.
Quote:
Because the PC has a 16-bit single-cycle incrementer, I'd expect there never to be a carry when fetching successive bytes using the PC. So I'd expect there's only one source of a page-crossing delay from instruction 7C - the addition of X. Are you sure that's not so?
Mystery solved BigEd
I think you're quite right. I was in an 8 bit frame of mind and neglected the 16-bit PC incrementer I have on the board! Here is the microcode now (as yet untested):
Code:
(fetch-opcode from the previous instruction)
B := *PC; PC += 1 # fetch low byte of abs address
PCL := B + X; B := *PC # Add X to low-byte; fetch high-byte of abs address
PCH := B + 0; USE(IC) # Add the Internal Carry (IC is set by B + X above)
DPL := *PC; PC += 1 # fetch the low-byte of the target address, 16 bit increment PC
DPH := *PC # fetch the high-byte of the target address
IR := *DP; PC += 1; END # fetch the next opcode; here PC += 1 is equivalent to PC := DP + 1 as a 16 bit operation.
Note: the operation PC +=1 performs a 16-bit increment of whatever address is on the address bus at the time and places the result in PC.
Six cycles, no conditional branching.
Ironically, this is less efficient than what I had before (since it does not save a cycle if a page is not crossed), but the aim here is compatibility. So this is in fact a better solution. Thanks for your comments BigEd. Very helpful!
While we're here, below is the microcode for TSB <zpg>
Code:
DPL := *PC; PC += 1 # fetch the zero page address
B := *zDP # fetch the target byte in zero page
B := *zDP; T := A AND B; SETF(Z) # Set the Z flag, re-read the target byte
T := A OR B # OR in the bits in the accumulator
*zDP := T # Store the result back in memory
IR := *PC; PC += 1; END # fetch the next opcode
Six cycles rather than 5.
I require one cycle to set the Z flag with an AND and another to set the correct bits through an OR. Since the busses are in use during the OR, a final cycle is required to write the result back to memory. Can't quite see how to do it in 5. What am I missing?
Cheers,
Drass.