For bank switch, trace debug, freeze, etc...
Whether it will work at all

(The idea I think is to detect three consecutive writes, using just a few gates, because that can only be the pushing of P and PC for an interrupt or BRK?)

I want to build a functional equivalent of that.
ftp://www.zimmers.net/pub/cbm/schematic ... index.html
But in a system where the bank has switched 64K.
The goal is to register the P, PC onto the stack in one bank
A service interupt in another.
Is the detection of 3 consecutive write cycles makes it possible?

Yes, I believe 3 consecutive writes is a unique signature. Watch out for RDY though - on a CMOS 6502 it can stretch writes.

Thank you.
I do this in 6510 so RDY probably should not bother.

I believe 3 consecutive write cycles is a reliable indication that an IRQ,NMI, or BRK is in progress. And your circuit looks right.

Another way to detect an interrupt is to monitor the address bus. Normally with 65xx the address bus will always increment following a SYNC cycle. The only exception is when an IRQ,NMI, or BRK is happening. In that case, the address will be the same one time. I mean the address during SYNC will be the same as the address during the following cycle. This is a reliable indication that an IRQ,NMI, or BRK is in progress -- and it works faster. The interrupt is detected before the writes to stack. You could switch banks before the writes if you want.

Here's the circuit. The XNOR gate looks at A0 to see whether PC incremented. The AND forces the output low in cycles other than those following SYNC.

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It is interesting .
But now I have 6510 without SYNC.