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PostPosted: Sat Jun 06, 2015 7:28 am 
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As I'm using an old NMOS 6509 I'm thinking about different memory layouts:

    Simply switching the whole 64kb with the MMU registers 00/01 - easy to implement, but the botched design with the registers 00/01 appearing everywhere making the address space non-continuous. Dr. Jeffyl, you said something about "the flawed but fixable 6509" (http://forum.6502.org/viewtopic.php?f=10&t=2997&hilit=6509#p33930) - are there really ways to fix that issue? Or was that a fix in a FPGA redesign?

    Using 00/01 to switch 16kb/32kb memory banks, e.g. CPU sees C000-FFFF part of a 256kb ROM, P0-3 select which 16kb of the ROM are accessible. As the 6509 doesn't have continuous memory space anyway, I could keep ZP,Stack and I/O in all memory configurations.

    Taking a completely different approach, which doesn't use 6509s features (but they surely will be re-used in some other way): Instead of banking in a larger window of 16-32kb, focus on the 6502 architecture and use banks of two pages (to allow for abs,X/abs,Y). That would mean CPU can do pointer arithmetic at 8-bit boundaries. Each window would require a set of adders so bit 9 can be calculated in. At my 2MHz speed there would be enough time (300ns TACC, 100ns RAM, that leaves 200ns - almost propagation delay of almost 10 times nibble adders), at higher speeds that would be difficult. And, of course, this would require quite some board space.


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PostPosted: Sat Jun 06, 2015 5:08 pm 
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Hobbit1972 wrote:
"the flawed but fixable 6509" (viewtopic.php?f=10&t=2997&hilit=6509#p33930) - are there really ways to fix that issue? Or was that a fix in a FPGA redesign?
I meant a redesign -- something that would allow us both to have the registers at 00/01 (because they're necessary for mapping control)... and also not have the registers at 00/01 (because they fragment the 1 MB space)! Here's how. Indirect-Y mode is mandatory when accessing extended memory via the registers, but a person would never need to use Indirect-Y mode to access the registers themselves. That means the problem would be solved if the select logic for accessing the registers themselves would look for address 0000/0001 and require that Indirect-Y mode not be in effect. That'd be easy to arrange in an FPGA design but it's not something you could retrofit to an existing 6509.

( Maybe existing 6509s do feature such logic. After all, it would've been easy for MOS to do it that way -- a minor change with major benefits! But the datasheet is vague, and I don't have a 6509 to test. Therefore I posed the question in this post, which is part of the thread MOS 6509 look-alikes. )

Quote:
Using 00/01 to switch 16kb/32kb memory banks, e.g. CPU sees C000-FFFF part of a 256kb ROM, P0-3 select which 16kb of the ROM are accessible.
Clever idea -- I like it!

Quote:
Instead of banking in a larger window of 16-32kb, focus on the 6502 architecture and use banks of two pages (to allow for abs,X/abs,Y). That would mean CPU can do pointer arithmetic at 8-bit boundaries. Each window would require a set of adders so bit 9 can be calculated in.
Another clever idea. I think I understand, but, to be sure, let me explain it back to you.

In the small map (64K) you have a page set aside -- let's say it's page $20 ($2000-$20FF). Your custom hardware causes page $20 to map to any desired page in the big map (1 megabyte?). For example, page $20 might map to page $113 ($11300-$113FF). But what do we do if indexing causes the CPU to output an address in page $21 instead? Your plan is to also have page $21 set aside. Of course it must map to page $114 for indexing to work -- and the adder you mentioned would compute $113 + 1 = $114.

The adder idea is workable, but the delay is a potential problem. There are alternatives. Since you already need some sort of register to hold the extended page address ($113), you could easily have another register to hold the $114. Software would pre-increment the value at the time both registers were loaded. If you used 74_670 IC's then the extra register would not require a lot of additional wiring. (For more on the '670, see the topic here.)

-- Jeff

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PostPosted: Sat Jun 06, 2015 5:32 pm 
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Dr Jefyll wrote:
Hobbit1972 wrote:
"the flawed but fixable 6509" (viewtopic.php?f=10&t=2997&hilit=6509#p33930) - are there really ways to fix that issue? Or was that a fix in a FPGA redesign?
I meant a redesign

( Maybe existing 6509s do feature such logic. After all, it would've been easy for MOS to do it that way -- a minor change with major benefits! But the datasheet is vague, and I don't have a 6509 to test.

I tested yesterday evening - sadly lda/sta ($00),y accesses the CPUs registers not memory.

Dr Jefyll wrote:
Quote:
Using 00/01 to switch 16kb/32kb memory banks, e.g. CPU sees C000-FFFF part of a 256kb ROM, P0-3 select which 16kb of the ROM are accessible.
Clever idea -- I like it!

TY :)
I wonder if there would be an easy way to switch between windows of 32kbROM+16kbRAM and 16kbROM+32kbRAM.

Dr Jefyll wrote:
Quote:
Instead of banking in a larger window of 16-32kb, focus on the 6502 architecture and use banks of two pages (to allow for abs,X/abs,Y). That would mean CPU can do pointer arithmetic at 8-bit boundaries. Each window would require a set of adders so bit 9 can be calculated in.
Another clever idea. I think I understand, but, to be sure, let me explain it back to you.

Yes, you got it. And brought a major improvement to it.


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PostPosted: Sat Jun 06, 2015 7:14 pm 
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Quote:
I wonder if there would be an easy way to switch between windows of 32kbROM+16kbRAM and 16kbROM+32kbRAM.
I've found that, with enough headstrong obstinacy, almost anything is possible! :D

Hobbit1972 wrote:
I tested yesterday evening - sadly lda/sta ($00),y accesses the CPUs registers not memory.
Is this a typo, Ralf? Based on my reading of the 6509 datasheet, you'd never code a lda/sta ($00),y. The operand could be from $02 to $FE, but $00 isn't useful. Here's a code example.

Code:
;Objective: fetch the value at $12345 (20-bit address)

ZPg_Ptr        equ $34 ;or whatever -- just an ordinary 65xx indirect pointer
6509_Ind_Reg   equ $01 ;special 6509 register at $01

lda #$45       ;bits  7-0 of "$12345"
sta ZPg_Ptr

lda #$23       ;bits 15-8 of "$12345"
sta ZPg_Ptr+1

lda #$01       ;bits 19-16 of "$12345"
sta 6509_Ind_Reg

ldy #0           ;no indexing in this simple example
lda (ZPg_Ptr),Y  ;use of lda (ind),Y triggers the 6509_Ind_Reg. Acc is left = contents of $12345

The suspected flaw is that this won't work if (for example) the value $12345 is replaced with any value ending in 0000 or 0001. Instead of accessing memory, the 6509 will access the special registers.

ETA: we need to access the special registers, but not with (ind),Y mode. In the code example I simply sta zero-page to update 6509_Ind_Reg.

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PostPosted: Sat Jun 06, 2015 7:47 pm 
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Dr Jefyll wrote:
Hobbit1972 wrote:
I tested yesterday evening - sadly lda/sta ($00),y accesses the CPUs registers not memory.
Is this a typo, Ralf? Based on my reading of the 6509 datasheet, you'd never code a lda/sta ($00),y. The operand could be from $02 to $FE, but $00 isn't useful.

Oh, yea, typo.... I meant ($02) and 02/03 containing 0000. :mrgreen:

Dr Jefyll wrote:
Code:
;Objective: fetch the value at $12345 (20-bit address)

ZPg_Ptr        equ $34 ;or whatever -- just an ordinary 65xx indirect pointer
6509_Ind_Reg   equ $01 ;special 6509 register at $01

lda #$45       ;bits  7-0 of "$12345"
sta ZPg_Ptr

lda #$23       ;bits 15-8 of "$12345"
sta ZPg_Ptr+1

lda #$01       ;bits 19-16 of "$12345"
sta 6509_Ind_Reg

ldy #0           ;no indexing in this simple example
lda (ZPg_Ptr),Y  ;use of lda (ind),Y triggers the 6509_Ind_Reg. Acc is left = contents of $12345

The suspected flaw is that this won't work if (for example) the value $12345 is replaced with any value ending in 0000 or 0001. Instead of accessing memory, the 6509 will access the special registers.

Yes, this flaw is not only suspected, but tested (see 6509-thread and my 6509 produced the same botched result). If ZPg_Ptr contains 0000 or 0001 - then access goes to register, memory (in writes) will contain what remains on the data bus (=in my case ZPg_Ptr address, $34 here).


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PostPosted: Sat Jun 06, 2015 10:15 pm 
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A slight side track: I thoughthe 6809 as made by Motorla, not MOS? I dont't know huge amounts about it so I might be wrong.


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PostPosted: Sat Jun 06, 2015 10:35 pm 
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6809, yes, made by Mot. Not the 6509 though.

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PostPosted: Sat Jun 06, 2015 10:46 pm 
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GARTHWILSON wrote:
6809, yes, made by Mot. Not the 6509 though.

Ahh ok. Forum posting late at night leads to silly mistakes :oops:.

Looking at the wiki entry it does seem to get slated for it's bank switching mechanism.
Why not use a 65816? Or is it a nostalgia thing?


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PostPosted: Sun Jun 07, 2015 10:12 am 
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banedon wrote:
Looking at the wiki entry it does seem to get slated for it's bank switching mechanism.
Why not use a 65816? Or is it a nostalgia thing?


Explanation of the nostalgia thing see here: http://forum.6502.org/viewtopic.php?f=12&t=3312 :)


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