Hello.
I am relatively new to this forum, please see my post in the Introduce Yourself section in General Discussions if you are not comfortable talking to a stranger .
Recently I started to build 6502 based general purpose microprocessor system or Homebrew Computer (I like this term more) just for the heck of it (and nostalgia is involved). More details about how am I going to assemble the system on the boards are here:
http://6502cpu.blogspot.com/2012/01/mkh ... -some.html
Can somebody please provide some expert advice about how I should lay out the pins on my CPU extension bus sockets and my I/O expansion ports sockets? Is there any recommended arrangement of pins? E.g.: if some pins should be neighbors, while some should be far apart and such kind of guidelines? I looked at the (in)famous S-100, but the pin out seems to be chosen at random on that bus.
Thank you in advance for your time.

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Marek Karcz
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"Don't worry. We've got our best people working on it."

Greets and welcome!

I personally like power at the far edges and keep the busses grouped together. For noise shielding, an entire row can be grounded, such as all the odd pins, making one side as ground. Might also want to put mroe grounds round a high speed clock to keep it from interfering with other lines, perhaps.

for my pinball mind, I am using the WDC RAM expander bus with some extra lines I need as a variation. (had pulled out more the R/W unqualified due to me wanting to use 65C22s beyond)

to look at the WDC one, look at their 65C02 development board and the schematic is on their website. westerndesigncenter.

Take a look, www.nightmarepark.com/6502.php the click on the pinball mind folder and get the schematic pdf in there.

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"My biggest dream in life? Building black plywood Habitrails"

Thank you for reply, I will certainly check these referenced materials. The tip with shielding clock pin is certainly a good one. I have 64 pins available on my bus, so I can spare quite many for ground shielding. I will need 16 address + 8 data + all control signals/clock plus my I/O decoder outputs (total of 8) plus IRQ input for CPU card slot ad output for other cards. Vectorized IRQ controller lines inputs will be going all to the I/O expansion bus, which has less pins (40) but I am not going to attach the whole address bus to it, just lower 8 bits. Each will have one input to vectorized IRQ controller and one from I/O decoder (chip select) plus CPU control signals. This leaves much less for shielding, but I think quite a few can be spared as well. I did not do the exact count yet.

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Marek Karcz
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"Don't worry. We've got our best people working on it."

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thank you for your response, Garth.
I already made up my mind about the architecture of my system to be organized around 2 buses, CPU and I/O, hence my question was about how to lay out these pins rather than the philosophy of the system architecture.
Your advice is great, however it simply promotes a different philosophy than I chose. Perhaps my future systems will follow your model.
My project will have little practical and more educational use. It has desired modular architecture, so I will be able to add to the system as my project progresses. I will mount several circuits on the same board with CPU, including clock, I/O address decoding, start-up reset and EPROM address decoder and EPROM memory. However RAM memory and RAM address decoding circuit I want to build as a separate CPU bus card, since I may change my mind about memory capacity and memory banking circuitry or build a brand new different RAM card in the future.
I use slow clock (CPU at 1.8 Mhz), therefore there should be no penalty performance wise. I have the prototype now wired
on the bunch of bread boards with big mess of wires and it so far worked fine. I do not have whole lot of
peripherals connected at this point, just UART and LCD and just base RAM with no banked RAM part yet (ran out of bread board space), nevertheless I do not expect any problems when I connect advanced I/O card based on bunch of 6522-s on my buffered I/O bus and banked memory and graphic chip on local CPU bus. When I say local CPU bus, I mean the non-buffered close to CPU card part of bus. The whole bus will not have very long wires (up to 20 cm total I believe, including wires leading from CPU to the bus expansion sockets and wires under the mobo connecting 3 sockets on that bus that I will have in total, and to the chips on memory and other CPU bus expansion boards. They are not spaced wide apart, I will keep them close.
The I/O bus will be a little more extended on the other side of mobo, however it will be buffered. The buffer chips will be put just past the last CPU bus socket and will amplify and isolate CPU bus from I/O part. Wires on that bus may be a little longer than on local CPU bus, because they will span over several (4-5) expansion sockets. My UART and LCD now are both connected to that buffered I/O bus with long wires between bread boards and both seem to work flawlessly. That bus will not have all address wires on it, just lower 8-bit part (I dedicated 256 bytes for each I/O device). I do not have oscilloscope to see the signal quality though and there may be some ugly interference (expected on the bread board with heavy parasitic capacitance), which should be much reduced when I solder the thing point to point with much shorter and thinner magnet wire.
Thank you for your input though.

With best regards...

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Marek Karcz
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"Don't worry. We've got our best people working on it."

Since your primer directly links to this forum thread:

To be honest Garth, I personally don't think it's very fair to say "don't run the buses off the board" and use serial interfacing and the VIA, and call it a day. Unless you're using wire wrap (time consuming, and high initial cost for sockets and tools, but easier to make changes) instead of making a PCB (defer the time cost for a monetary cost + sockets), the ability to add new high speed parallel I/O is very difficult without having an expansion bus.

I can only speak for myself, but one goal of me making a 65xx computer is to have something which I can interface parallel I/O with, just by adding a device to the 65xx bus. This is possible with near-zero prop-delay thanks to your creative incomplete address-decoding scheme that you placed on the primer. I'm not saying I2C, SPI, or interfacing using the VIA/PIA's output doesn't have it's place, but there's at least three things that come to mind:

1. If I wanted purely serial I/O besides a VIA, I would've gone with a microcontroller instead of learning how to interface to the 6502.
2. On a similar token, some devices are parallel by nature, and sometimes interfacing through serial I/O expander becomes difficult timing-wise, especially if the parallel device has control signals that must be asserted beforehand.

I'm not the analog designer by trade, you are . I think it would be nice if an example parallel bus that could work at high speeds be added to the primer, while still exercising caution. One doesn't even have to bring all the address lines out- just enough for I/O-device select, CLK, data, and power. I've never taken an RF course, but I'm certainly willing to take a chance on making my own 65xx/65816 parallel bus- or use an existing generic bus such as Wishbone and create a workable physical layout. PC-104's may also be a candidate. The 65SIB is giving me ideas on how to design such a bus as well.

I'm happy to discuss my reasoning further in DM (too far ahead in the future for me to make public promises now).

Of course, the alternative COULD be to just have the PCB remade, but... . I personally think it's better to add incrementally while still deferring the time cost of wire-wrap.

EDIT: Yes, I see Jeff Laughton's single cycle I/O trick, so there's no penalty for accessing data through the VIAs. It doesn't solve the problem of adding more fast parallel I/O. VIA also doesn't help interface 8-bit devices which require more than two control signals, or an 8-bit device with registers, such as a 6845 (example) .

Quick reply before bedtime.

I would not take the MPU's buses off-board as well, although I sort of did this when I added the SCSI host adapter to my POC unit. What you might want to consider is a parallel expansion bus that is driven by a pair bus transceivers or similar and devise a protocol for selecting the particular I/O device that you want. It is conceivable that you could do this with a 65C21 or 65C22, either device which can support 16 bit parallel I/O. Please give it some thought. I think you'll end up with a more flexible and reliable arrangement.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Marek, cr1901,

Bear in mind that some people are more cautious than others, and that some people will be quite OK with trying to debug and improve a not totally reliable first effort. Bear also in mind that very many of the early home computer designs, running at 1 or even 2 MHz, did take their busses off board, if only for a single point-to-point expansion.

So, when you see people saying "I wouldn't do that" you need to calibrate your own sense of what's worth trying with theirs: they might be more cautious than you, or they might know what is doomed to fail. If their background is industrial product design, you'll probably find that they want a lot of predictability, reliability and margin in whatever they make.

Cheers
Ed

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?