WDC recommends driving both PHI2 and your main system clock direct from your oscillator instead of via the PHI2O output of the CPU with modern designs, and indeed if I drive my main clock from PHI2O instead of direct from the oscillator I see random issues with memory not working as expected.

Why is this though? I would've thought that since legacy systems worked this way it would still work fine, at least at 1Mhz.

Looking at the difference on my scope there appears to be only 4ns difference between the two, I would've thought that at 1Mhz that wouldn't really make much difference?

It does seem strange. You've tested two variations of the circuit, and one fails while the other appears to work properly. But experience has taught me to question (apparent) success in a puzzling case like this.

I could be mistaken, of course, but I suspect you either have a design error or have made a wiring error when implementing the design. Either way, it's possible to end up with a project that works, but only just barely. Ordinarily 4 ns wouldn't make a difference, but in this case it does. Just thinking out loud...

Can you post a schematic, please? And what's your construction technique -- is it a solderless breadboard?

cheers
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The construction is on PCBs I got made at OSHPark.
The schematic is here: http://imgur.com/QRmXdhb

The design is probably quite terrible, I am going to redesign and start again because I clearly didn't do a good job this time. things like the 74HC85N are probably not helping with regards to speed, as well as being cards & backplane design on account of the eagle free limitation. my next one will be a single board.
I got this thing made a while ago, before I had posted here for some advice against the ISA slots etc, so it's probably surprising that it works at all.
What is extra weird to me is that it didn't work properly even at 1Mhz with the above schematic, after cutting the traces and wiring the clock signals to all come from the oscillator it now works perfectly even with a 5Mhz oscillator.

I'm sure the problem is just that I've done a hilariously bad job of making this thing.

Huh. I don't notice anything conspicuously wrong here. BTW on this forum you're allowed to make attachments with your posts -- which is more convenient (and more permanent) than using a third-party site such as imgur. Also BTW, some folks find that Eagle schematics are more legible without the use of color. I've taken the liberty of making a monochrome rendition:A few faintly bothersome points:

The schematic includes the signal names CLK and CLKIN. CLK drives two inputs on IC5 (the NAND), but I wasn't able to find the origin of this signal -- did I miss it? The obvious guess is that it comes from pin 39 of the CPU. Is it possible that you and Eagle have had a misunderstanding?

The I/O circuitry is not included on this diagram, and I presume it's located on a separate card. Which leads to the question, was the I/O card disconnected when you performed your tests? If the tests involved the I/O card then it'll be best if you supply that schematic too.

Should we ignore the Rockwell part # R65C03P3 and assume you're using a WDC 'C02? The logic that generates RAM_CSL could be simplified, but what you've got there doesn't seem wrong.

I kind of like how you've used the 74HC85. And you're right, it's no speed demon; but at low clock rates it should be fine. In future you might wanna consider an 'AC85 instead.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

CLK comes from the PHI2O from the CPU, I didn't really do enough labelling on the schematic but I've now double-checked eagle and it definitely was connected
The CPU is indeed a WDC, I was too lazy to change the part number when I used the Eagle Library for that.

the IO card schematic is listed below, I've had it plugged in the whole time of the testing etc.

With regards to the Ram CS and the 74HC85, I intended to have $0000-CFFF occupied by ram, hence the RAM_CSL and RAM_CS2 but at the moment I've only got one chip installed, what is the best way to simplify this though?

As for the 85, I'm unable to find any 74AC85's so i'm probably going to have to use a different decoding circuit if I want to go higher speed.

When I get the chance I'll take some screenshots from my scope and post them.

For a 32k ram occupying the lower half of memory, you can use A15 as the chip select. It doesn't need any extra logic.