Something that bothers me while I'm designing a paper version of the DMA controller... How is it possible for the 6502 to clock out an address, read/write signal and read/write data within a single clock cycle? Assuming that the 6502 needs to retrieve registers from the datapath, clock them into temporary registers, place them on the bus, I'm not sure how its physically possible for the 6502 to send an address and read the data in one clock cycle- considering any register to register transfer requires waiting for the clock to latch the data. Even if the processor uses both edges of the clock, I'm not sure how all the temporary registers can be clocked in the middle of phi2 when no transitions occur.

I know the modern 6502s are pipelined, but even when the pipeline is flushed, a memory cycle can be accomplished within a clock cycle. So I doubt that is the full answer.

Additionally, is there any literature which explains how the processor is capable of delaying control signals by a non-integer number of clock cycles? For example, I built a toy
CPU for class. I specifically remember that the address rwas calculated by the ALU on one clock cycle, was latched into the address bus register on the leading edge of the NEXT clock cycle- at which point the read signal was synchronously placed onto the control bus by the control unit. The data was then latched during the leading edge of the next clock cycle, while read was deasserted. unfortunately, I don't remember how we dealt with the fact that deasserting read simultaneously will invalidate the value from memory on e bus. reReading the data therefore took multiple clock cycles. But the 6502 can assert control signals in the middle of a clock cycle.

Would the 6502 work with synchronous RAM?


On that note, I do not think one memory xfer per bus cycle will be possible on my dma design, but... I'll upload my paper circuit tonight.

This topic may help: viewtopic.php?f=4&t=2632
The 6502 seems to have a lot of transparent latches though, not just edge-triggered registers. Ed can probably tell you a lot more, from the Visual6502 project.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I think the trick is that the 6502 sets up all the necessary actions for a given clock cycle during the previous clock cycle. This is why a NOP takes 2 cycles.

Arlet's core works with synchronous RAM, and to do that he's had to jump through a couple of hoops. I still find it a little confusing, although I'm very grateful that it works! For a real 6502 to work with synchronous RAM, I suspect you'd need to break the access cycle into two, either by clocking the RAM faster or by clocking the 6502 slower. But this is off the top of my head - I'm sure others can give better answers.