We often discuss the hair-thin margins implied by WDC's datasheet timings: a 14MHz clock is a 35ns clock phase, and yet a number of output timings are given as 30ns worst case.

It would be a great service, I think, if anyone with a suitably fast scope or logic analyser could post photos of traces from their working 6502 or 65816 system - it doesn't even have to be a fast-running system. All we need is some idea of the loading on those chip outputs, and the timing of them.

Several of us suspect that the 30ns figure will not be seen in practice.

It's possible that an instruction such as JMP will be a worst case for address outputs, because the high byte of the address must appear in the cycle after it's read. See
http://www.visual6502.org/JSSim/expert. ... a&steps=20


But for control outputs such as RnW, Sync or VPA, VDA, VP, I see no such difficulty - the outputs should be direct from a phi1-gated latch. Timing will depend on load (and voltage, and temperature.)
See
http://www.visual6502.org/JSSim/expert. ... 0&zoom=6.0
and
http://www.visual6502.org/JSSim/expert. ... 4&zoom=2.1

Cheers
Ed

Edit: here's the path from the bottom bit of the databus to the 8th bit of the address bus - pretty much has to cross the entire chip:
http://www.visual6502.org/JSSim/expert. ... 3.8&zoom=1