At the moment I'm using a 74HC138 to divide my address space into 8k blocks. This is OK for I/O and ROM (2x 8k ROM), but not for 32k SRAM.

AFAIK the 74hc138 has no open collector outputs, so direct wired AND is not possible, but could I use some diodes to create a wired-AND connection to create a single /CS signal for the SRAM chip?
Like this example:
http://www.elv.de/module/community_expertenwissen/bilder_popup.aspx?id=97
Because I need the line "LOW" if one of the 4 inputs is LOW, otherwise HIGH if all are HIGH.

I know that there a much simpler solutions to make address decoding with a 74HC00 and a 74HC04 for 32k RAM, 16k ROM and much I/O (like Garth's Primer), but I want to understand how things work.

Mario.

OK, I could use A15 and invert it to create the chipselect for RAM and 74HC138, but then I have the same problem dividing my 8k ROM into two 4k chunks.

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How should I know what I think, until I hear what I've said.

You can get away with diode logic, certainly up to 2MHz (I've seen a sideways RAM solution for the Beeb which use the technique, I think successfully) but you should look out for how fast/slow they go and how much drive you get. It might be that you can drive CMOS inputs but not TTL.

BTW, I think you mean to link to this picture:

from this article - the link you gave needs a previous visit or something.

Cheers
Ed

AND will work for TTL most times, but not OR, unless the pull down R is really low, like 390 ohms or less, and even then I wouldn't trust it.

The nice thing about the '138 is the three enables; two low and one high. The 74LS145 1-of-10 decoder has open collectors that can be used for wired AND. It doesn't have an enable but the MSB input can be used as an active-low.

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"I am endeavoring, ma'am, to create a mnemonic memory circuit... using stone knives and bearskins." -- Spock to Edith Keeler

That circuit would probably run at much higher clock rates if Schottky diodes are used. For example, this diode has a 4ns recovery time and an 800mv forward drop. However, in a wired-OR configuration you'd have to be aware of parasitic capacitance and its effect on circuit low-to-high transition time. Also, with a single diode approaching the cost of a gate, it wouldn't be a particularly economical solution.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Mario, resistor pull-ups or pull-downs tend to be very slow unless you're willing to make them pretty heavy. For example, to get 20ns rise time with a 50pF load, you would need 390 ohms (as Richard said), and pulling that up or down to the other rail is over 10mA per resistor! To make it worse, you have to add the reverse-recovery time of the diodes, the time taken by the '138, and the rise time of the 138's output. The '138 is kind of a slow IC to start with, because of the many levels of logic in it. The 74AC00's worst-case propagation delay with the same load is about 8ns total.

If you still want to go that way, be sure to use Shottky diodes, especially for pulling down, since silicon ones may not let the voltage get low enough for a valid logic 0.

If you still want to use the '138, instead of putting another gate after it, you would do better to have a different, parallel address-decode setup for the RAM, to reduce the total delay to the various memory and I/O ICs. Also, make sure you have the phase 2 qualifying things correctly. It is imperative that you not allow writes to RAM when phase 2 is low; but the I/O ICs need their selects to be valid and stable before phase 2 rises. On a 6502 system (but not '816), you can leave phase 2 out of the ROM circuit.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

As I inferred above...


Average prop time for the 74AC138 is about 6ns at 5 volts. Worst case is 10ns over the full commercial temperature range. I'm using a 74AC138 in POC V1.1 and the circuit will easily run at 12.5 MHz. You're probably thinking of the 74HC138, which is kind of slow in comparison. I won't even mention the 74LS138. The 74F138 is slightly faster than the 74AC138, but draws quite a bit more power.


Actually, all selects should be valid before the rise of Ø2. That is mandatory, of course, with most 65xx I/O silicon. Ø2 should never be used to qualify chip selects, as doing so needlessly limits the performance of the circuit. The '816 has the VDA and VPA outputs to tell address decoding hardware when the address bus is valid. The 65C02 doesn't generate false address bus states, so nothing special needs to be done in that regard. NMOS silicon isn't quite as cooperative and really should be avoided, except for restoring old hardware.

What has to be qualified by Ø2, as Garth notes, is writes to memory and I/O. D0-D7 contain valid data only when Ø2 is high. This is especially important with the '816, which presents the A16-A23 address component on D0-D7 while Ø2 is low.

If performance is that much an issue it's time to look at using programmable logic for address decoding. A typical PLD of almost any type has a prop time pin-to-pin of 10ns or less. You can't achieve that with discrete gates.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Much less...
Multiple levels of logic in a FPGA/CPLD, since they are 'on-die' and nanometers apart, can easily outperform individual TTL logic IC's performing the same address decoding for example no matter what the TTL family.

This is a "yawn factor" in the Programmable Logic" section. But sometimes enthusiasts need a wake-up call.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

You posted just after I started writing and looking things up.


According to my NSC books, the max at 5V, 25 deg C for the HC138 is 35ns, and for the AC138, it is 15ns.


If the I/O is 65-family ICs, particularly the '22 and the '51, the R/W\ needs to be valid and stable before phase 2 rises. They still won't write to their registers until phase 2 rises, so there's no risk of writing to the wrong registers because of the address not being valid and stable yet.


Two cascaded levels of simple 74AC is close, but I wish 74ABT was available in the simple ones. I do remember a lot of PALs and GALs though that had maximums of 25ns or more. I haven't looked at the market recently, but I remember someone saying the PALs and GALs were being dropped by most manufacturers.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

See the attached TI datasheet. When were your National books published?


Right you are. I seldom think in terms of 65xx I/O devices when I write this stuff, as I haven't used any of them for a long time.


74ABT is available for a lot of gates, bus drivers, etc., which helps with cascaded logic. However, one PLD can do the work of a lot of discrete gates without incurring substantial prop time penalties.


Atmel continues to produce GALs in PDIP and SMT packages, with ratings down to 7ns. For what we do, a 10ns part is more than sufficient. Altera, Atmel and Lattice also make small SMT CPLDs that run in the 10ns or faster range. Altera has one called the MAX 7000 in a PLCC-44 package, running on 5 volts and with a 10ns pin-to-pin prop time. It has 64 macrocells and would be perfect for the sort of application about which we are talking. Digi-Key stocks it.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

So let me see if I understand what this difference between HC and AC means. I'm thinking of using the little brother of the '138, the dual 2-to-4 '139. For the 74HC139, the data sheet gives me average of 11 ns, whereas the 'AC139 has 6.5 ns. That's (very roughly) half. So does this mean I could cascade two ACs (technically, two halves of one '139) with about the same speed as one HC?

Is there a catch? The Internet says something about "noise" and "oscillation" with ACs, but how important is that when you use the same chip? And isn't this what we put capacitors all over for?

(Scenario for using both parts of a '139 -- low address space (0000 to 7FFF) is 32k or RAM. High space is divided into four 8k blocks by one half of the '139; three of them get 28c64 ROM 8k chips, the fourth is divided again by second half of '139 to drive four I/O chips, say, one ACIA and three VIAs or something. Just as a real-word example.)

Generally speaking, yes. Propagation times are essentially additive at the clock speeds we use. I have to question, though, why you'd consider such a scheme. It sounds as though you may be using a complicated solution to handle a simple problem.

Incidentally, bear in mind that "average" performance is for a device running at nominal voltage (e.g., 5 VDC) in a 25° C environment. Timing analysis should always account for the worst-case scenario that is likely in your application, such as lower than normal voltage (CMOS switching performance decreases with operating voltage), higher chip temperature due to close proximity to heat-generating sources, etc. Also, in a random sample of devices, you may get some that are near the maximums, even though being operated at nominal voltage at 25° C. Should you end up cascading two such devices you may end up with a DOA circuit if the clock rate is sufficiently high, even though the average prop time says it should work.


What I think you are referring to is "ringing," which is a circuit phenomenon in which the voltage oscillates around the low or high level for a (very) brief period following a state transition. It has nothing to do with 74AC logic in particular.

Circuit ringing becomes a problem with faster silicon of any type, mainly because the output transition time from one state to the other is extremely short (sub-nanosecond in some cases). Due to unavoidable reactance present in all electrical circuits, the effect of a level transition at a connection's far end slightly lags the same transition at a chip's output. As the far end of the connection "catches up" with the chip's output the voltage overshoots and then undershoots before stabilizing, an effect that may persist for many nanoseconds in extreme cases. If the ringing is sufficient in magnitude, the input of the device connected to the circuit may be momentarily driven into an ambiguous area of its switching characteristic, causing undefined behavior at its output(s).

Corollary to ringing is ground bounce, which is a short-term oscillation at the ground pin of the affected device. As input levels are sampled with respect to ground, ground bounce can also cause a device's input to be momentarily driven into the ambiguous area of its switching characteristic. Ground bounce is often attributed to the presence of unwanted reactance and resistance as well, again unavoidable in a practical design.

Ringing cannot be totally prevented in fast circuits but can be dampened in various ways to avoid undesirable side-effects. The number one antidote to ringing (and ground bounce) is short and direct connections. The fact that breadboard layouts use long curving wires is the reason why such units typically can't run very fast—the large amount of reactance present virtually guarantees that severe ringing will occur.


The decoupling capacitors are there to keep switching transients from getting into the common power source and to help mitigate the effects of ground bounce, although the latter is strongly influenced by the "ampacity" of the ground connections to the individual devices. In addition the use of short and direct connections from device output to device input, ringing can be subdued with damping resistors or Schottky diode arrays at the input(s) of the affected device(s)—tactics that shouldn't be necessary with most homebrew designs.

If you are building your unit on a PCB, a four-layer design with inner power and ground layers can do a lot to minimize ground bounce, as well as the overall noise layout. Four-layer also facilitates a more compact layout, leading to shorter inter-device connections. On a wire-wrap unit, use heavier gauge wire for power and ground, and avoid a serial power and ground distribution layout.


The $0000-$7FFF range can be decoded with A15 alone, since A15 will always be low in that address range. In other words, hook /CS of your RAM to A15. RAM will be selected as long as the address is less than $8000. A0-A14 would go to the corresponding inputs on the RAM.

I think you are needlessly constricting your available RAM. Allocating 8KB for I/O is, in my opinion, wasteful—worst-case scenario is any one I/O device needs a page. I allocated 4KB for I/O in my POC V1.1 unit, which is enough for 16 devices, and currently have eight I/O slots decoded (with a single 74AC138). I presently have five I/O slots occupied and don't anticipate using anymore in this design.

Also, what do you plan to do with 24KB of ROM? I was able to pack POC's entire BIOS (which includes SCSI drivers) and a full-featured M/L monitor into an 8KB ROM space, and there are some bytes left over. I could see using 16KB of ROM to load a language (e.g., Lee's EhBASIC), but 24KB?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

This looks like a rule of thumb, along with a handwave, so I'll ask the two questions that spring immediately to mind: First, under what circumstances do propagation times not behave in an essentially additive fashion. And second, when propagation times aren't essentially additive, how do they behave? In short, when does this rule not apply, and what happens when it doesn't?

On the other hand, I've made several 2 layer boards than comfortably run at 100 MHz. One of them was the sandbox board, shown here: viewtopic.php?f=4&t=2453

From what I know of the TTL/CMOS family of IC's, temperatures and power supply voltages are the main affectors of propagation delay variations.
So to answer your question, if all the IC's share the same board and power supply, the temperature factor could most likely be negated. The power supply will become more of a factor depending on how large the design is and how poorly the power lines are routed.
Also, read the datasheet and understand you have MIN's and MAX's.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

That board has several good things going for it.

• it's small
• all the connections are very short
• the highest speeds are all contained inside the FPGA
• the ground plane was well implemented for a 2-layer board, with lots vias to ground on the other side where it would otherwise have been interrupted

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?