I am currently designing my own implentation of the 6502. All I have left to design is the control matrix. I am confused how instructions like INX take only two cycles. Shouldn't the cycles be like this: cycle 1-Load alu input register a with value of x register. Cycle 2-increment a input register and output into x register. Cycle 3-nop to reset the control matrix counter. Does the 6502 combine the 2nd and 3rd cycles. All of the microprocessors that I have studied before output only nop as the last cycle of each instruction.

Hmm, I've never heard of this NOP idea. What happens in the 6502 is that instruction fetch is overlapped with the final cycle of the previous instruction, unless it was a memory write:
1. instruction fetch
2. Steer X into ALU, set it up for increment
3. [overlapped with following instruction fetch] write result to X

See for example http://www.visual6502.org/JSSim/expert. ... f&steps=26
or for more detail http://www.visual6502.org/JSSim/expert. ... re=idb,dor

Cheers
Ed

I have one more question. In instructions like LDA 0200, FF how does the 6502 take one less cycle when the addition is not over one page. Can someone explain in the cycles of that instruction?

The ALU is used for address computation here, and is eight bits wide. The carry output from the ALU is used to indicate that the compute address is incorrect, and thus the address being read is wrong. This read cycle is also used to correct the high byte of the address, and thus the following cycle is used to fetch the correct value. AIUI, this only applies to the NMOS 6502, and not to the more recent CMOS versions, though I could be wrong here.

I hope that this explanation helps.

-- Alastair Bridgewater

How does it take one less cycle? Does the alu increment the control matrix counter to skip a cycle?

If by " LDA 0200, FF" you mean there's FF in X and you're doing LDA $0200,X, I think the idea is that it just does not add the extra cycle if the indexing did not make it cross a page boundary.

From an older post: The 6502 does however have minor pipelining and it has many cycles where more than one operation takes place. An example given in WDC's programming manual (page 40 in my edition) is ADC#, which requires 5 distinct steps, but only two clocks' time:
Step 1: Fetch the instruction opcode ADC.
Step 2: Interpret the opcode to be ADC of a constant.
Step 3: Fetch the operand, the constant to be added.
Step 4: Add the constant to the accumulator contents.
Step 5: Store the result back to the accumulator.

Steps 2 and 3 both happen in a single clock. The processor fetches the next byte not knowing yet if it will need it or what it will be for. Steps 4 and 5 occur during the next instruction's step 1, eliminating the need for two more clocks. It cannot do steps 3 and 4 in one clock because the memory being read may not have the data valid and stable any more than a small set-up time before phase 2 falls and the data actually gets taken into the processor; so step 4 cannot begin until after step 3 is totally finished. But doing 2 and 3 simultaneously, and then doing 4 and 5 simultaneous with step 1 of the next instruction makes the whole 5-step process appear to take only 2 clocks.

Another part of the pipelining is the reason why operands are low-byte-first. The processor starts fetching the operand's low byte before the instruction decode has figured out how many bytes the instruction will have (1, 2, or 3). In the case of indexing before or without any indirection, the low byte needs to be added to the index register first anyway, so the 6502 gets that going before the high byte has finished arriving at the processor. In the case of something like LDA(abs), the first indirect address is fetched before the carry from the low-byte addition is added to the high byte. Then if it finds out there was no carry generated, it already has what it needs, and there's no need to add another cycle to read another address 256 bytes higher in the memory map. This way the whole 7-step instruction process requires only 4 clocks. (This is from the next page of the same programming manual.)

The 2-clock NOP has to do with the 2-clock minimum for the instruction step counter. I don't know why that is, but maybe the visual6502 website would help. Commodore had a patent on a process they used in the 65CE02 that allowed them to eliminate virtually all the dead bus cycles and make at least 30 op codes take just one clock. There were not very many 65CE02's made, and the '816 was a better upgrade to the 65c02 than the CE02 was, so I'm glad to have that.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

(I don't much like your example Garth, although I do know you've used it before, because the "steps" are not steps at all. If anything, they are actions, but I think it doesn't help to clarify unless you put one tick per line, or at least only number the actual ticks)

It's worth noting that the 6502 sequencer is not a counter. It's nearly a shift register, but not quite. Think of it as a state machine or a collection of state bits. Study the "State" column from visual6502 which shows which bits are active (active low, I think) - see
http://www.visual6502.org/JSSim/expert. ... 2,t3,t4,t5

Cheers
Ed

Good explanation.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?