I started doing a little bit on the successor to my sandbox board described in this thread: viewtopic.php?f=4&t=2453

Biggest difference with previous version is that the CPU (either 6502 or 65816) will be connected directly to an SRAM chip, rather than connected to the FPGA only. The big advantage is that this frees up a lot of pins on the FPGA, which can then be used for other purposes. There's also a disadvantage: the FPGA now shares the memory bus with the CPU, so they will have to take turns. I've debated this issue for quite a while, but in the end I decided that having the extra pins was worth more than some small speed gain. And if speed is really important, it's always possible to use the 6502 soft core in the FPGA.

I've attached my schematics so far, and also a bit of the dense layout, just to try it out.

The SRAM is a Cypress CY7C1049DV33, 512kB, 10 ns device in SOJ packaging. The SOJ has wide enough pins that I can fit a 6 mil trace in between, which greatly simplifies routing the bus. The FPGA is a Spartan 6.

The rest of the schematic is still open. I'm planning on a ADV7391 video generator (can do component, S-video and composite), a sound chip, UART, dual USB host port, micro SD (maybe SD instead), and serial Flash (also used for FPGA)

When the design is finished, I will make extra boards for anybody who is interested. These will be available to forum members at cost of materials. If anybody is interested in certain features, let me know.

This is a great opportunity for anyone interested in getting their feet wet with FPGA's! This design could start from the simplest, but then could also go very advanced. And with your help on this forum, much can be learned.
The only intimidation factor for most would be the soldering of the surface mount devices. Are you offering prebuilt/tested boards as well? If so I would imagine some kind of extra fee should be expected.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Yes, I was planning to offer prebuilt/tested boards to reduce the intimidation factor of 0.5 mm QFP devices, but also to make it cheaper and easier to acquire the components all in one time, and spread out the shipping cost over a larger order. If there's enough interest, I'll get a stencil, so the assembly should be fairly quick.

Are you going to try to manually solder the FPGA or are you going to rig up a make-shift reflow setup? I know that it is possible to hand-solder 0.5mm pitch devices, but the process is tricky and not for those not possessing keen eyesight and steady hands (that would be me ).

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

For one or two boards, I can do it by hand. The biggest problem is not the soldering itself, but making sure all the flux residue is gone. Especially under the chip it's hard to clean.

On the previous version I also soldered the chip by hand:


My trick is to use a piece of desoldering wick, soak it full of solder, and push it against the pins to transfer a bit of the solder to the pins. A bit of flux helps to avoid bridges.

My eyesight isn't so good as it used to be, but I manage with a pair of cheap reading glasses from the drug store.

I recently purchased a heated ultrasonic cleaner on ebay for the purpose of cleaning off flux residue. Using isopropyl alcohol seems to do a decent job. But it's not as good as what's in your pics.

BTW, why is the removal of flux so important anyway? Just for looks?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Some flux is electrically conductive or corrosive. Recently I had problems on a board, and when I removed a large TQFP I noticed there was still wet flux under the chip that had corroded away the vias.

The outside is easy to clean, especially with special flux cleaners.