Asynchronous Bus Controller Logic Design

[kc5tja]

http://www.falvotech.com/Kestrel/async-bus.html

The link above resolves to a document containing the proposed bus interface system for the ForthBox Kestrel computer kit I'm designing. It provides a 68000-like asynchronous bus interface to the otherwise very synchronous 65816 bus interface signals. It provides zero performance hit for suitably fast devices, while it automatically generates wait states for slower devices. The bus can be clocked at arbitrary speeds; for any given transaction, the CPU will slow to the speed of the currently addressed device.

If people are interested, I can market chips (both bus controller and DTACK-generators for devices) designed to couple to implement this bus system for you. Please let me know what you think.

[leeeeee]

Very nice, this makes the 65816 much more like the 68008 which I've used before.

The only addition I can suggest is make RDY = !AS & !DTACK. For the cost of this one gate you have the complete four phase system, no more worries about keeping !DTACK shorter than the next clock edge.

The only other thing I can think of is cycle time for some devices is near, or more than, twice the access time so how would read/modify/write in this case be handled?

Cheers,

Lee.

[kc5tja]

leeeeee wrote:

Very nice, this makes the 65816 much more like the 68008 which I've used before.

Thanks.

Quote:

The only addition I can suggest is make RDY = !AS & !DTACK. For the cost of this one gate you have the complete four phase system, no more worries about keeping !DTACK shorter than the next clock edge.

This is true; however, I wanted to ensure a minimum latency design; 12MHz is sufficiently close to the 65816's 14MHz rating that I don't want to push things to the edge. With discrete component logic, even that circuit might be too much.

Quote:

The only other thing I can think of is cycle time for some devices is near, or more than, twice the access time so how would read/modify/write in this case be handled?

Your question is hard for me to parse. I don't understand what you're asking. I can't even guess at what you're trying to ask.

Can you rephrase the question?

[leeeeee]

The cycle time for a device is the minimum time between successive accesses. E.g. with 150ns DRAM the access time is 150ns as you would expect but the cycle time, the time from the start of one access to the start of the next, is often 250 to 300ns.

Go here .. http://www.arstechnica.com/paedia/r/ram ... rt2-1.html .. for DRAM timing notes.

I've just been lookign at the 65816 timing and it seems that any 16 bit access to a slow device could cause a problem as the next access cycle starts on the next clock after the last cycle has finished. At 12.6MHz this would mean less than 40ns from the end of the last cycle to the start of the new, possibly not enough time.

Most of the time you would get away with this but it will fail unexpectedly and often not repeatably.

Hmmm not very clear, but it is 01:53 here 8^)=

Cheers,

Lee.

[kc5tja]

leeeeee wrote:

The cycle time for a device is the minimum time between successive accesses. E.g. with 150ns DRAM the access time is 150ns as you would expect but the cycle time, the time from the start of one access to the start of the next, is often 250 to 300ns.

Ahh, I see what you are saying now.

This would be solved exactly as it would be with a 68000 -- you hold off the DTACK signal until you know it can be satisfied. If this means disabling bus drivers temporarily, letting the chip complete the last cycle, then that's the job of the DTACK signal generator. Consequently, the complexity of the DTACK signal generator for that device is directly proportional to the complexity of the device it's bound to.

--
Samuel A. Falvo II

[leeeeee]

Of course, that makes sense, then the added complexity is there only if needed.

Could !DTACK be open collector driven so that additional devices could be wire-ored onto it, or would that slow it down too much?

I'm going to try a minimal 65816 design with one ACIA, (D)RAM and ROM soon. I want to try a maximum memory design using 4 x 4MB 30pin, 60ns, SIMMs and a fastest possible design with 1MB of 15ns cache RAM.

Cheers,

Lee.

[kc5tja]

leeeeee wrote:

Could !DTACK be open collector driven so that additional devices could be wire-ored onto it, or would that slow it down too much?

I remember reading somewhere that WDC decided to make /IRQ and /NMI regular logic signals because otherwise response times were too slow for the higher clock speeds. I suspect the same kind of thing would happen with /DTACK. That being said, maybe if you time things just right, you can make your DTACK-generator bring DTACK low one cycle early, and rely on the R-C time constant to delay it just long enough to get the proper timing. I'm not sure.

Depends on how good you are with your logic design skills, I guess.

[leeeeee]

I've done some typical case delays for your circuit for standard LS and ALS 74 series parts. Times are LS/ALS(ns)

From VDA/VPA to !RDY is 33/10ns
From DTACK to RDY is 23/8ns

If you change RDY to be !AS & !DTACK the times become ..

From VDA/VPA to !RDY is 41/13ns
From DTACK to RDY is 31/11ns

This gives you ..

80-33-23-10 = 14ns max for !DTACK (LS)
80-10-8-10 = 52ns max for !DTACK (ALS)

.. assuming an 80ns (12.5MHz) clock cycle for your circuit or ..

80-41-31-10 = -2ns max for !DTACK (LS)
80-13-11-10 = 46ns max for !DTACK (ALS)

.. with the extra AND gate. Ok so it won't quite work at 12.5MHz using LS parts.

Cheers,

Lee.