This question has been bugging me for a long time, and Google never seems to point me to anything resembling an answer. This seems like a knowledgeable place to ask, even if a bit OT.

So I understand the basics of DRAM: Row selection does a relatively slow sense operation to fill buffers and to reassert the values into the storage capacitors, then column selection reads from the buffers out to the pins.

ROMs would do the same demultiplexing for address selection, but given that regular masked or fuse-based PROMs should (as far as I understand) just be a simple wire from input to output, why are they slower than DRAMs?

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WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

For the two ROM technologies you asked about, DRAMs are much slower. See the 1973 Intel Memory Design Handbook.

If compared to modern DRAMs, i.e. DDR SDRAMs, these ROM technologies have comparable random access speeds, but dramatically slower sequential access speeds. The implementation of the ROMs you mentioned is designed to specifically support random accesses. The multiplexer required to connect the sense amps to the memory cell, even if it's a static mask-programmed value, is a complex device in its own right. There's at least one logic layer for each address bit in the ROM in order to retrieve the desired memory cell and connect it to the output drivers. There's no free lunch in IC design, and that random access multiplexer represents a significant amount of delay.

A modern DRAM has a random access delay of around 10 clock cycles. Sequential access is significantly faster from the point where the "row" has been loaded from the array into the row buffer and the column selector, i.e. starting point in the row, has also been preset. The associated multiplexers are faster than the ROM's because they generally only have half the number of bits, and the entire row is read from the DRAM array in parallel.

If a ROM was designed for sequential access on a row of the array, and because it doesn't have to refresh the memory cells, it would be faster than a DRAM. Modern NAND Flash provides very high speed sequential access. It's not quite as fast as a modern DRAM, but it appears to be giving SDRAM a run for its money. Like DRAM, it uses a paged access mechanism better optimized for sequential access. Hence its extensive use in high-density Solid State Disk Drives (SSDD).

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Michael A.

To nail down a particular generation, I'm thinking of Amiga and 90s PC where there was an explicit copy of Kickstart/BIOS from ROM into RAM, for speed purposes. (I'm assuming this still happens on PC.)

So ROM chips, at least of that era, typically didn't have row/column pin multiplexing, thus forcing a full-width address decode per access? Or they just never bothered with using row buffers if they did pin-multiplex? It seems that with the spatial locality of running machine code, row buffers would still make a lot of sense there.

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WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

Agree that the row buffers and the shift registers starting at the desired column would produce fast sequential access times. However, the trade is a level of complexity that is not warranted unless there no other alternatives like copying from ROM to RAM and executing from RAM.

DRAM, on the other hand, has to periodically refresh the memory cells. There's not a better solution than implementing a row buffer other than implementing more than one row buffer and the refresh counter on chip. Thus, the DRAM can prefetch the next sequential buffer, steal a few cycles to perform the refresh when the current read cycle terminates, or have a row buffer or two free to deal with random accesses.

The internal complexity of the DRAM has always been higher than that of other memory types. Lest we forget, programming of PROMs or EPROMs is performed one memory cell at a time. It is very likely that the single cell addressability provided by most ROMs, although good for random access, is also driven by the requirements for high current and voltage programming of the memory cells.

Although I never used fusible link PROMs, the Intel Memory Design Handbook that I linked to previously describes the process for programming those devices. Apparently, they required current through each individual bit to program. Modern devices program Flash cells at least a byte at a time.

The spatial locality of an assembly language program is probably higher than that of a HLL-based program. To take advantage of spatial locality, the ROM would need row buffers whose width is some fixed length. If the accesses hit near the boundaries of the row buffers, the program will experience significant delays when the next sequential buffer is required unless there is a prefetch mechanism included to make some assumptions regarding program flow and prefetch the next row. To reduce the probability of this occurring, the row buffers could be doubled in length. But this solution only exacerbates the problem when it does occur. Under certain conditions, the ROM (and DRAMs) begin "thrashing" their row buffers.

All this additional complexity starts to make these devices behave more like cache memories. Since the cache memory is required to accomodate the speed differential between the DRAM and the processor, adding that level of circuit complexity does not solve the ROM memory access time issue in an economically sensible manner. The KISS principle applies to ROMs: yields and profits will be higher for less complex devices.

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Michael A.

That was mostly because of the differing memory widths. PC BIOS ROMs were only 8 bits wide and Amiga kickstart was 16 bits wide so copying to 32 bit wide RAM could halve or even quater the access times.

Lee.