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 Post subject: 6502 bus buffering
PostPosted: Wed Apr 28, 2004 4:08 pm 
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Joined: Wed Apr 28, 2004 3:58 pm
Posts: 12
Hi,

I'm half way through designing and building a simple 6502 based expandable SBC for use as a general purpose controller.

The basic system consists of a 160x100 eurocard with a 6502 clocked at 2MHz, 1x 8K SRAM (6264), 1x 8K EPROM (2764), 6522 VIA and not much else apart from glue logic. Pretty basic as it goes. It already runs up on breadboard without too much hassle.

One small problem is that the system needs to be expandable and therefore I need to take the bus off the board (via a R/A DIN41612 connector). At worst case, there are going to be bus runs of about 20cm and up to 5 additional 6264 SRAMs and 4 6522 VIAs running off this bus.

Will this run without buffering stably, if not; what is the best way to buffer the data, address and clock lines? Also, should I buffer the bus on the CPU card or all cards?

Cheers all.


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PostPosted: Wed Apr 28, 2004 5:12 pm 
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Joined: Wed Sep 10, 2003 4:11 am
Posts: 16
Location: Finland
Hi.
You can't drive that many chips without buffering.
http://www.xs4all.nl/~ganswijk/chipdir/f/buffer.htm 74 series chips should be more or less suitable, pick one that fits best to your needs.
Good luck on the project.


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PostPosted: Wed Apr 28, 2004 6:32 pm 
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Joined: Fri Aug 30, 2002 1:09 am
Posts: 8541
Location: Southern California
> You can't drive that many chips without buffering.

This may have been true of the old NMOS processors especially when some loads would be 74LS instead of CMOS, but the CMOS processors running at only 2MHz can drive a ton of CMOS loads.

I took some numbers on 65c22 VIAs which I believe have the same drivers as their manufacturers' processors.

I found the WDC VIA to be able to pull down to a valid TTL logic-low level with about 24mA, and up to a valid TTL logic-high level with about 40mA. Even if you had all LS loads, that's still at least 15; but your memory and VIA inputs and any CMOS logic inputs will require virtually no current except to charge the input capacitances-- an trivial job at 2MHz.

I found from experimentation that the Rockwell VIAs can pull down to a valid TTL logic-low level with about 40mA, and up to a valid high with over 10mA. Just trying to pull down with the pin shorted to +5V, I got over 100mA. (Not wanting to damage the part, I did this shorting test at only one pin at a time and for just long enough to get a reading.)

My workbench computer which you can see at http://www.6502.org/users/garth/projects.php?project=1 has 8 things on the data bus, and the voltages still go virtually all the way to 0V and 5V, with waveforms as square as my 20MHz oscilloscope is able to display.

The STD-bus automated test equipment setup I did at my last place of work, which you can see at http://www.6502.org/users/garth/projects.php?project=6 , had 12 things hanging on the bus, including 7 memory ICs, 4 I/O ICs, and the 74LS buffers that went only to the STD bus backplane, not to the memory and I/O ICs.

Note: At the time of this writing, there's something wrong with the website and the ATE URL takes you to the workbench computer page again. Hopefully it will be working when you get this message.


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