Few days ago i was clearing up some ideas that i had for my sbc, and i decided that i will not use the additional latch to interface my "pic to ps2/i2c" interface mcu that i described a while ago in a topic.
But i already soldered the latch and got it working. Since i have a functioning latch, with her own address, i was wondering how could i use it, so i thought maybe i could build a random generator. The simple way would be to just read the value from the 4060 counters that i used for clock generation, and baud rate generation, but that is kinda like cheating. I would like to have all the 8 bits filled with random values, but i only have space for 1 max 2 14 pin ic, or 1 16 pin ic, and not room for any kind of cpld. So any ideas how a simple random generator could be made?

With the space that you describe, 2 14-pin DIPs max, an 8-bit Linear Feedback Shift Register (LSFR) would be your best solution. It could consist of a '164 8-bit serial-in, parallel-out shift register, and an '86 quad XOR gate connected as an XNOR. See the attached BMP/PDF of the schematic.

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Michael A.

Thanks, i might try to modify it a bit to be able to receive some other inputs...

If you're into HDL, or even if you aren't (you can still create a symbol and put it in your schematic) Xilinx has some good info and code in xapp884.


I used it in my project and it works well.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

What if i instead of +5V on U2:D i put the baud clock of 2.457MHz and as the main clock, the cpu 4MHz clock?

Dajgoro:

Apart from the obvious periodic metastable condition that will occur whenever the high pulse of the 2.4756 MHz clock violates the setup/hold time of the shift register's 4 MHz clock, an unpredictable pseudo-random count will be the result of your suggested modification and that effect may be perfectly acceptable. However, I suspect that there will be a fair interaction between the two clocks because the half period of the 2.4576 MHz clock (203 ns) is not greater than the period of the 4 MHz clock (250ns).

The counter will count in two different sequences as the shift register clock rising edge hits on a 2.4576 MHz high or low. When it is high, the shift register will count in accordance with an XNOR count sequence, and when it's low, it will count in accordance with an XOR count sequence.

The reason that I chose to use an XNOR in the feedback path is that the system reset pulse will clear the shift register, and with an XOR feedback, the counter will not count: 0 XOR 0 => 0. The XNOR count sequence will not hang in this situation. Contrary to the note I pasted into the schematic I sent you in an earlier reply, the XNOR sequence ranges from 0 to 254 instead of 1 to 255 as I noted. It is the XOR sequence which ranges from 1 to 255. The XOR sequence locks up on 0, and the XNOR sequence locks up on 255.

Your modulation concept is a good concept, but I would recommend using something like the TTL transmit data of a UART output instead of the 2.4576 MHz clock. It is too close in frequency to the shift register clock, and there may long periods of time when the half cycle width of the 2.4576 MHz does not satisfy the setup and hold requirements.

Better to build it for operation within normal design parameters, than to lose several hours trying to figure out why the random number generator is not working as expected.

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Michael A.

Thanks for the reply.
I will post again when i wire this circuit up.