I think I've read the data sheets correctly, but assuming an NMOS 6502, am I correct:

That during phase 2 low, the data bus is tri-stated but the address bus is still driven by the 6502? If so, it's damned inconvenient of it... If not, life gets much easier for my video design.

Cheers,

Neil (off to read the data sheets again)

That's correct. Putting the address out earlier eases the timing requirements on the memory a bit. In a write cycle, you must have the address valid and stable a short amount of time (the setup time) before the part is allowed to go into write mode. If the address is being formed while the part is going into write mode, you have a precarious situation where writes to unintended addresses could occur. If you are not pushing the speed limits of the parts involved, you could add tri-state buffers to the address lines, using the processor's phase 2 output signal to enable the buffer, and add a phase 2 rising-edge delay (but not a falling-edge delay) for the memory and other I/O ICs in order to meet the timing requriements.

Some I/O ICs like the 6522 need the address and R/W lines valid and stable a minimum amount of time before phase 2 rises, or they won't work at all. I had to make the above delay circuit to make 6522's work on an I/O expander board for our son's Commodore 64. You can see the diagram and pictures of the board at http://www.6502.org/users/garth/projects.php?project=7

I'm not pushing timings too badly, but I'm interleaving CPU access and video access on phase2 high and low respectively. A single 32k*8 static ram is addressed by the CPU on ph2 high, and by the video controller - an ATMega8 microcontroller - on ph2 low. The cpu drives through 74act541 (or equivalent) so the processor address then is stable when the phase changes - data is latched into the ram on the rising edge of r/~w so no problems there. The video controller, at appropriate times, updates a count onto the ram address bus through resistors; when the 541 is three-stated there's enough current through the resistors to drive the ram for the video display.

Had the 6502 a bus disable then I could have dispensed with the resistors and the 541s, and dropped the circuit to only eleven ICs and four fewer packages on the PCB. It fits on half a eurocard - just! - at present, but hasn't been built/tested yet. I'll probably knock it up with DIL chips first

Perhaps one of the CMOS variants has a bus enable? I've seen something somewhere...



Neil (somewhat bemused by the fact that he's just designed a computer which has a video controller smarter and faster than the main processor...)

> I'm not pushing timings too badly, but I'm interleaving CPU access and
> video access on phase2 high and low respectively.

The Apple II did this kind of thing.


> Had the 6502 a bus disable then I could have dispensed with the . . .

WDC's 65c02 does have a BE (bus enable) input. It's pin 36 on the DIP, and pin 40 on the PLCC. It's also fast enough that you wouldn't have to divide your 8MHz dot clock down; in fact, if your other parts and your construction can handle it, the 65c02 can go twice that fast-- 16MHz. I guess I should have mentioned the BE earlier even though you did specifically bring up the old NMOS 6502. The NMOS was also slower, had fewer instructions and quite a few bugs and quirks, and took a lot more power.

And the Tangerine, which is what I learned 6502 design on, and I've designed several SBCs - a couple of which ran for ten years before they were replaced - which had to genlock to broadcast video... they worked the same way. But it's been a long time since I designed one



Yes, I noticed it on the 65c02, but I have an NMOS 6502B. 2MHz is fast enough for road-runner wire. Also, I changed the design back to plan A; an eBay win of 241s that I'd given up on arrived, and they're rather handy as A/B bus selectors. Same theory, just detail change.

Thanks,

Neil