See the attached image.

Is the green box region (tDSR+tHDR) the period of time where the 6502 expects valid data on the data bus?
Or is that tACC? If it's tACC, how long do I need to have the data lines stable prior to phi2 rise for 6502 to do a valid read operation?

And the green box (tMDS+tDHW) the period of time where the 6502 guarantees valid data is asserted for a write?

Thanks,

Eric

The green box is the time during which the data must be valid on a read cycle. It must be valid at least tDSR before the falling edge of PHI2 until at least tDHR after.

The red box is the time it guarantees that data will be valid during a write cycle: at most tMDS after the rising edge of PHI2 until at least tDHW after the falling edge.

tACC is a strange one. It's giving you the latest point that the address will be valid: at least tACC before at least tDSR before the falling edge of PHI2. It's an odd specification, because it references the address, which the 6502 controls, to the data, which it doesn't. If you have a nice fast memory system and provide data earlier, the address is not going to magically become valid earlier too.

I think they've specified that because it's the important number when you're designing the memory system. You've got at most tACC to provide data after the address becomes valid.

Yes, exactly. (And, stated that way, I wouldn't say there's anything odd about it, John, although I do see your point that the 6502 doesn't control arrival of the data; it merely has a requirement of how soon data must arrive).

ebadger, for further info, you may perhaps wish to refer to my Visual Guide to 65xx CPU Timing. The animated "rubber band" diagrams are intended to offer insight into timing margins and the tradeoffs between them.

-- Jeff

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