Hope these pics are helpful. The leads do extend down very slightly, so that should help with either manual soldering or a reflow oven/hot plate.

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Regards, KM
https://github.com/floobydust

Thanks!

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Bill

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The socket is a 3M product:

P/N 8432-21A1-RK-TP

Mouser, DigiKey and others stock it.

_________________
Regards, KM
https://github.com/floobydust

It's only recently - in spite of pushing fifty years of building stuff - that I've had to consider EMI regulations (a video amplifier in a metal case in an apparatus room, or a robot three miles underground, doesn't really care if it doesn't interfere with itself). But most recently I've had the joy of having to meet international regs for EMI and I can state that it *is* possible to run a processor at 32MHz on a two layer board and still meet the specs.

Most of the emitted radiation - up to 3.5GHz IIRC - is not from the board itself but from things fastened to the board: external LEDs and opto-sensors, leads to strain gauges and switches and motors etc. For confidentiality reasons I can't go into detail but a ground pour on the component side and a power pour on the other side, a number of chip inductors in series with external connections, and attention to decoupling. One thing to bear in mind is that with some processors - e.g. the STM32L range and no doubt others - the drive speed of the output pin can be controlled. There is no sense in setting it faster than you need to.

Other, faster, parts require a four layer board to keep the emissions under control and where possible, use of spread-spectrum clock signals which 'smear' the noise wider in frequency bit lower in amplitude.

For my 'play' boards I don't really care about the radiated emissions but I do try and keep good practice - though I'm sure there are as many definitions of that as there are engineers. I prefer to use double sided boards with ground on the component side and Vcc on the other; traces go left right on one side and up down on the other (which means there is a # mesh of power across the board) and I insist on chips facing the same way if at all possible - pin 1 is top left or top right depending how it fits.

Here's a recent example, with the fill planes turned off (or it becomes even more incomprehensible) to show the idea:

Neil

Picking this up, even though it's old: I don't think it adds "capacitance" but it does add "inductance". That's the effect of making the return path deviate from the signal path.

I don't think it makes the return path deviate - the return current will naturally try to avoid deviating, it won't take a worse route just because you provide it with one. But I can imagine that - in the absence of a good close return path - the return current for the edge of a pulse could follow along a ground pour up to the point it's interrupted, and then essentially crash hard into that interruption, spreading waves of EMI across the ground pour while it looks for an alternate route to follow. I do wonder whether it may sometimes be better to force it to follow a chosen path, rather than giving it what initially looks like a good return path but which later suddenly turns bad.

There is a great animation of something similar in one of Robert Feranec's videos, it is quite dramatic. They say that when this happens the ground pour turns into an antenna, and depending on its size compared to the wavelength of your signal's edge, it can cause a lot of external radiation as well as interference in the whole of the rest of your circuit.

I will see if I can find the video to link. However I find that while the "interview" videos are interesting to watch, these aspects are not always fully or consistently explained, and I've sometimes seen different experts in his channel saying apparently quite different things. So I must be misunderstanding the nuances.

I think I worded it badly. What I meant to say was that the "cut" in the fill would add inductance, and not having the fill at all would increase the cross-sectional area of the loop that the forward and return paths collectively make, relative to even a fill with a "cut" in it. That thing with signals "crashing" into a pour edge is most likely only relevant at frequencies considerably higher than we have any business thinking about. But my main point was that capacitance has no bearing on the situation, especially if the pour and the signal trace are on opposite sides of a 2-layer board (and thus several times further apart than a signal trace would be to a ground plane on the same side).

I would generally prefer to have full ground and power planes where practical, since that means you don't even need to think about stuff like that at the speeds we tend to play with. That should be quite easy to achieve with a four-layer board, which I think are quite practically intermediate between 2-layer and 6-layer boards in terms of pricing. Complex signal routing could be eased by making holes in the power plane but leaving the ground plane intact. There are noncritical applications where a 2-layer board is easy to get right, and that would help to control costs, especially when the board is large. Six-layer boards are something we shouldn't need, unless maybe we're doing something truly ambitious.

It's worth noting that the clock frequencies we typically work with are in the same ballpark as the Intermediate Frequency of a superheterodyne radio, which amateurs have been successfully building long before professional-quality PCBs became available to the average amateur. Transition edges do contain harmonics significantly in excess of this, but we're still in the realm of motherboard-sized PCBs that you can treat as a "lumped element" because the wavelength of the signal greatly exceeds the physical size. Most of the SBCs we build are substantially smaller than that.

Ah yes I'm sorry, I think I did misread and thought you were saying this inductance was causing the deviation - my mistake.

From what I've heard, the thing about board thickness increasing the distance from the ground plane is important and may mean that any form of ground plane on a thick two layer board is a bit pointless. I've also seen advice that power planes are a potential liability and you may be better off with two ground planes, and ground vias where signals swap sides of the board. But as you say, I don't know at what edge rate this becomes the case, and it's one of the things I've seen conflicting advice on.

I'm actually disappointed that my current project didn't suffer any problems due to this sort of thing, as I was planning to try making a four layer version afterwards to fix any issues. I suppose AHCT parts are not fast enough to cause the problems.

I think the HC and AHC parts have quite slow signal edges by design, and in fact AHC is designed specifically to match the HC slew rate and drive strength while having most of the faster propagation time of AC parts. So the AHC parts begin their output transitions sooner, but should have similar high-frequency effects as HC. It makes them very friendly to suboptimal PCB layouts.

It's a little bit like how HC logic was designed to be as fast as LS logic, but with the inherently better drive strength, input impedance, and power consumption of CMOS technology, thus removing nearly all of the fanout limitations that LS logic laboured under. Then HCT added TTL level compatibility to that, so could be used as a direct individual drop-in replacement for LS.

Curious: at RF frequencies, a power plane effectively _is_ a ground plane... or so I was taught.

In a lot of our products, we find we need four-layer board - internal power and ground - and segmented ground fills tightly stitched through to the ground around RF parts, plus sundry other measures, to meet the EMI requirements up to 5GHz... testing is costly.

Neil

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

A bit late I know, but you might consider using the last revision of the PATA cables. They were 80 conductors on 40 way IDC connectors. In the flat cable every second conductor was ground. Almost 40 other conductors to use for signals.