I bought a Bus Pirate last year, and recently richarde borrowed it. He's just sent me these traces from the pins of a BBC Micro's 6502 - these timings are therefore typical and don't replace the need to study the spec when designing a system.



However, it's interesting to see what's happening in a typical working system. We note that the phi1 and phi2 signals are indeed (just about) non-overlapping. We think the Bus Pirate is sampling at 100MHz, so there's a quantisation of the edges, and of course the true sample times may be slightly jittered. If anyone can provide traces from an actual logic analyser that would be great.

(This is an NMOS 6502, normally clocked at 2MHz)

Cheers
Ed

Thanks. It's interesting to see that the R/W\ line actually went down before the address lines changed, strengthening the case for making sure that writing to RAM is qualified by phase 2.

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http://WilsonMinesCo.com/ lots of 6502 resources

Yes, well spotted. In this particular design the RAM subsystem is used for video output during phase 1 so that qualification probably happens naturally.

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x86? We ain't got no x86. We don't need no stinking x86!