The 6510/8500 CPUs are NMOS, afaik.

Is it right that NMOS outputs are pulled up permanently by an internal transistor which behaves like an internal pull-up resistor?

Is it possible without damaging something to pull _down_ one of these outputs (address line) from external without using AEC?

Of course this is not possible when the output is a CMOS totem pole. And of course it is _not_ possible to pull one of these outputs _up_.

Is it possible that C64/C128 users have replaced their NMOS 6510 CPU with a CMOS CPU?

Thomas

The only "replacement" is the SuperCPU (a 65816 circuit); nothing else works because the 6510A is not pin compatible. Additionally, the 65C02 gets rid of all the undocumented opcodes that programs like GEOS depend on (or, at least, used to depend on).

Concerning the other questions, I'll let those more familiar with the relevant technologies answer them.

I don't know the answer, but I don't think you'll find the pull-up is purely like a resistor. There's no equivalent circuit given in the datasheet, but I think it was normal to use an NMOS transistor to pull up, which would get you to a MOSFET threshold voltage below supply. From the datasheet giving output voltage as minimum 2.4V, I don't think there's any resistive assist to bring the output to the rail.

By way of illustration, Google gives a google books result with a pad driver circuit for NMOS, page 142, figure 7.5

Thank you for the replies. So it looks like there's a real transistor to pull up the pad.

I strongly suspect so. You could perhaps measure the current through a succession of resistors to see how hard it tries to pull things up, and how successful it is. Starting with large resistors, of course!

It sounds like you have a plan in mind, which somehow can't make use of AEC - care to share?

(By the way, within the chip, normal logic gates and inverters will normally have a depletion-mode transistor for the pull-up, which isn't a resistor as such, but does draw some current even when the output is being pulled down, which is why NMOS uses so much power compared to CMOS. But output pad drivers would normally not use that technique.)

I have and I will, as soon as it is running But it is very C64-specific.

The problem with this plan is not that I cannot make use of AEC but the long time of T_AED and T_AES (see 6510 datasheet). When I really wait for 120 ns before taking over the bus I run out of time easily.

This evening I'll try to solve another bug an possibly after that I can explain what I'm going to do.

Sorry to be late joining the discussion -- is your project still under way? To force an address line low, the first option to consider would be simply to insert a tri-state buffer (74xx125, 74xx368, 74xx244 etc) or an AND (74xx08) or mux (74xx157) into the circuit. But to patch in the new chip you'd need to break the connection between the CPU pin and whatever it connects to; is that a problem? -- is that why you're enquiring about shorting the pin low?

If the duty cycle is slight, and it's just a single address line you're shorting (not several), then localized heating of the CPU die (the pullup transistor) will probably be tolerable, and pulling the line low as you suggest may be a workable (if inelegant) solution. Admittedly it is asking for trouble -- like overclocking, it breaks the rules -- but if you're willing to accept some risk (of damaging the CPU) then have at 'er! The device you use as the external pulldown will need to be able to sink enough current to give a valid logic low, and to add minimum noise it should connect as directly as possible to the CPU ground pin and address pin.

I'm tempted to speculate about what it is you're up to: some scheme to alter memory mapping, evidently -- to provide an alternative set of interrupt vectors, perhaps?

NMOS outputs use a totem-pole circuit, with a pull-up and a pull-down transistor. Since they were designed to drive TTL logic, the pull-down transistor is large and can sink a fair current, while the pull-up transistor is small and can only source a small current. Since both transistors are MOS devices, they will appear as resistances when turned on and for small currents will be able to pull the outputs all the way to the supply rails.

While a TTL or 74HC output will sink more current than the NMOS pull-up transistor can source and will thus pull the output low, this will result in excessive current drawn from the output and will probably damage the chip eventually.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

First I can confirm from what I saw and measured that everything is as you guys told me. A preliminary result of the work can be found here: http://skoe.de/kernal/kernal-cartridge.pdf

Please don't redistribute it, because it's incomplete may may still contain flaws.

There's another question: Why does the pull-up FET in the 65xx seem to be much "weaker" than the pull-down FET, although both of them occupy similar space on the die (seen on a die photo)? The effect is that H-edges are _much_ slower than L-edges.

Thomas

Thanks you your response. The 6502 is an NMOS IC. Does it have p-type FETs at all?

Oops. No. The behavior is typical, but this is not what's happening in the 6502.

The pad drivers in the 6502 use an n-type FET to pull up the signal. As the output voltage goes up, the gate-source voltage goes down, and the drain-source resistance goes up, which causes the edges to be slower.

Thank you!